Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate
Reexamination Certificate
2003-06-09
2004-08-31
Lee, Hsien Ming (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having schottky gate
C438S270000, C438S574000, C438S578000, C438S579000
Reexamination Certificate
active
06784036
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to methods for making field-effect transistors.
2. Description of the Related Art
FIG. 1
is a schematic diagram of a conventional field-effect transistor which has a HEMT structure. The field-effect transistor includes an i-type InP substrate
1
, a channel layer
2
composed of i-type InGaAs, an electron supply layer
3
composed of n-type InAlAs, a barrier layer
4
composed of i-type InAlAs, a stopper layer
5
composed of i-type InP, a cap layer
6
composed of high concentration n-type InGaAs, a gate electrode
7
, a source electrode
8
, and a drain electrode
9
.
In the field-effect transistor shown in
FIG. 1
, a two-dimensional electron gas (not shown in the drawing) is formed between the channel layer
2
and the electron supply layer
3
. The barrier layer
4
reduces an electric field applied from the gate electrode
7
, thereby improving the gate breakdown voltage. The cap layer
6
, which decreases the contact resistances of the source electrode
8
and the drain electrode
9
, is provided on the barrier layer
4
with the stopper layer
5
therebetween. The stopper layer
5
functions as an etching stopper in the process of removing the cap layer
6
. The gate electrode
7
is provided on the exposed stopper layer
5
after the cap layer
6
is removed, and the gate electrode
7
includes a fine gate section
7
A which substantially contributes to the gate operation of the transistor and an over-gate section
7
B which decreases the resistance in the gate electrode
7
.
Next, the formation process of the gate electrode
7
will be described.
FIGS. 2A and 2B
are schematic diagrams illustrating the formation process of the gate electrode
7
.
FIG. 2A
is a sectional view of a region corresponding to the region A indicated by the broken line in FIG.
1
.
As shown in
FIG. 2A
, the gate electrode
7
is formed using a resist pattern composed of first to third resist layers
10
to
12
. The resist pattern includes the first resist layer
10
for determining the pattern of the fine gate section, the third resist layer
12
for determining the pattern of the over-gate section, and the second resist layer
11
disposed between the first resist layer
10
and the third resist layer
12
, the second resist layer
11
being side etched so that the third resist layer
12
protrudes like an overhang.
The patterns of the first resist layer
10
and the third resist layer
12
are formed, for example, using electron beam exposure, and the pattern of the second resist layer
11
is formed by etching such that over-etching occurs in the transverse direction in the etching step performed after the pattern of the third resist layer
12
is formed.
As electrode materials, for example, a Ti layer
7
-
1
, a Pt layer
7
-
2
, and a Au layer
7
-
3
are deposited over the resist pattern thus formed. Since the second resist layer
11
is side etched, the individual electrode materials are separated between the interior of the resist pattern for forming the gate electrode and an unnecessary section over the third resist layer
12
.
When the resist layers are removed, the unnecessary gate electrode materials over the third resist layer
12
are also removed, and as shown in
FIG. 2B
, the gate electrode
7
is produced.
In field-effect transistors, in order to improve the high frequency characteristics, gate electrodes must be miniaturized, and such a demand has been increasing.
In order to form gate electrodes accurately, resist patterns for forming the gate electrodes must be formed accurately.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a gate electrode accurately.
The present inventor has carried out research and found that cracking occurs in resist patterns for forming gate electrodes.
This will be described with reference to FIG.
3
.
FIG. 3
is an enlarged plan view which shows an end of a gate electrode and which shows a state corresponding to the state before the gate electrode materials are deposited in FIG.
2
A. In
FIG. 3
, the same numerals as
FIG. 2A
are used for the same parts, and the second resist layer
11
under the third resist layer
12
is indicated by a broken line because the second resist layer
11
is side etched so as to retreat from the edge of the third resist layer
12
.
As is obvious from
FIG. 3
, the third resist layer
12
located at the outside periphery of the resist pattern is cracked at a corner of the tip of the gate electrode. The cracking of the resist layer occurs in the development step of the pattern of the first resist layer
10
(fine gate section) or in the subsequent rinsing step, and in these steps, expansion and contraction are considered to occur rapidly in the first resist layer
10
(and also in the second resist layer
11
or the third resist layer
12
), resulting in the cracking. Additionally, the cracking of the third resist layer
12
extends from the region protruding like an overhang under which the second resist layer
11
is side etched to the second resist layer
11
beneath, and also to the first resist layer
10
.
If gate electrode materials are deposited on such a resist pattern in which the cracking has occurred, since the gate electrode materials are also embedded in the cracking, the embedded gate electrode materials may remain after the resist layers are removed, resulting in short-circuiting due to contact with another gate electrode of an adjacent field-effect transistor. Even if the embedded gate electrode materials are removed in the process of removing the resist layers, they may be redeposited on the surface of the chip, resulting in short-circuiting.
Moreover, if the resist pattern is cracked, a fatal flaw may occur in the gate electrode having the over-gate section. For example, since the planar shape of the over-gate section is deformed due to the cracking in the resist layer and a deviation occurs in the overlap of the over-gate section and the fine gate section, stress applied from the over-gate section to the fine gate section becomes nonuniform. Thereby, nonuniform stress occurs in a portion of the fine gate section in contact with the semiconductor layer, and for example, an electric field due to the piezo-effect degrades the transistor characteristics. If the stress applied to the fine gate section is excessive, the gate electrode itself may collapse.
The cracking of the resist pattern at the corner of the over-gate section occurs when a multi-layered resist structure is used in which a plurality of development steps are performed and the resist pattern includes a pattern of the fine gate section and a pattern of the over-gate section protruding like an overhang. Based on the finding described above, the present invention has been achieved to avoid cracking in the resist pattern.
In one aspect of the present invention, a method for making a semiconductor device includes forming a resist pattern having a multi-layered structure by performing a plurality of development steps, the resist pattern including a first opening corresponding to a fine gate section of a gate electrode and a second opening placed on the first opening, the second opening corresponding to an over-gate section which is wider than the fine gate section and having a cross section protruding like an overhang, in which every angle of the second opening at the tip of the over-gate section is more than 90 degrees; and forming the gate electrode provided with the fine gate section and the over-gate section by depositing electrode materials on the resist pattern. A typical example of this structure is shown in FIG.
4
. As is obvious from the drawing, in a pattern
20
of the over-gate section, all the corners at the tip thereof have angles of more than 90 degrees. Consequently, stress at each corner is scattered, thus preventing the resist pattern from being cracked.
In another aspect of the present invention, a method for making a semiconductor device includes forming a resist pattern having a mult
Makiyama Kozo
Ogiri Katsumi
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