Method for making power chip scale package

Details Method for making power chip scale package Method for making power chip scale package

2005-03-01

2005-03-01

Smoot, Stephen W. (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S123000

Reexamination Certificate

active

06861286

ABSTRACT:
A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.

REFERENCES:
patent: 4783428 (1988-11-01), Kalfus
patent: 4878108 (1989-10-01), Phelps et al.
patent: 5192681 (1993-03-01), Chiu
patent: 5381105 (1995-01-01), Phipps
patent: 5969411 (1999-10-01), Fukaya
patent: 6006981 (1999-12-01), Madrid
patent: 6689640 (2004-02-01), Mostafazadeh
patent: 6762067 (2004-07-01), Quinones et al.
patent: 20020139235 (2002-10-01), Nordin et al.

Affiliated with

Also associated with

Rating

Method for making power chip scale package does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for making power chip scale package, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making power chip scale package will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3369947