Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2000-08-31
2002-05-21
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S157000
Reexamination Certificate
active
06391693
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a polysilicon thin film transistor and method for manufacturing the same, more particularly to a polysilicon thin film(hereinafter “POLY-TFT”) capable of reducing leakage current and method for manufacturing the same.
BACKGROUND OF THE INVENTION
Thin film transistors are generally used for switching devices in the liquid crystal displays. Among the thin film transistors, the POLY-TFT has a relatively smaller size and faster operation speed, compared to the conventional amorphous silicon thin film transistors(a-Si-TFT).
When the POLY-TFT is applied to the liquid crystal display, it is possible to obtain thin and small modules. Further, a means for switching at an array substrate and a drive IC at a printed circuit board can be formed simultaneously thereby reducing manufacturing costs.
Herein, a top gate method in which a gate electrode is laid on an upper portion of a channel layer is frequently used in the conventional POLY-TFTs. However, the POLY-TFT according to the top gate method requires a number of masking processes.
Accordingly, there has been suggested a bottom gate method that requires less masking processes than the conventional top gate method.
As shown in
FIG. 1
, a buffer layer(not shown) is formed on a glass substrate
1
and a metal layer is deposited on the glass substrate
1
. A metal layer is patterned in some portions thereof thereby forming a gate electrode
2
. A gate insulating layer
3
is deposited on the entire glass substrate
1
in which the gate electrode
2
is formed. A polysilicon layer is deposited on the entire gate insulating layer
3
and patterned to cover the gate electrode
2
thereby forming a channel layer
4
. An insulating layer is deposited on the channel layer
4
and the gate insulating layer
3
. Thereafter, the insulating layer is patterned according to a back-exposing method thereby forming an ion stopper
6
. A source region
5
a
and a drain region
5
b
are formed at both sides of the ion stopper
6
by implanting impurity ions into the channel layer
4
.
Another metal layer is deposited on the resultant, and some portions of the metal layer is patterned to be contact with the source and drain regions
5
a
,
5
b
thereby forming a source electrode
7
a
and a drain electrode
7
b.
The POLY-TFT according to the bottom gate method does not require any masking process for forming the ion stopper
6
. Therefore, one masking step may be reduced, compared to the conventional top gate method requiring the masking step for producing the ion stopper
6
.
However, a relatively high drain electric field is maintained even in the off-state, since a distance between the source region
5
a
and the drain region
5
b
of the POLY-TFT according to the bottom gate method is very small. Therefore, a large quantity of leakage current is generated in the off-state.
SUMMARY OF THE INVENTION
Accordingly, it is one object of the present invention to provide a POLY-TFT capable of preventing the leakage current in the off-state.
It is another object of the present invention to provide a method for manufacturing POLY-TFT capable of reducing the number of manufacturing steps.
To accomplish the objects of the present invention, in one aspect, the POLY-TFT comprises a substrate; at least two gate electrodes formed on the substrate; an insulating layer coated on the gate electrodes; a channel layer formed on the gate insulating layer to cover the entire gate electrodes and made of polysilicon; an ion stopper formed on the channel layer corresponding to the gate electrode; impurity regions formed on the channel layer at both sides of the ion stopper; and source and drain electrodes contacted with outermost regions among the impurity regions respectively, wherein the outermost impurity regions are source and drain regions and the region between the gate electrodes is an auxiliary junction region for compensating an ON current.
In another aspect, the present invention further provides a method for manufacturing the POLY-TFT comprising the steps of: forming a plurality of gate electrodes by depositing a metal layer on a substrate and by patterning the structure; forming a gate insulating layer on the plurality of gate electrodes and on the substrate; forming a channel layer by depositing an amorphous silicon layer to cover the plurality of gate electrodes and by patterning some portions thereof; forming an ion stopper on a selected position of the channel layer corresponding to the gate electrode according to a back-exposing method; implanting impurities into both sides of the ion stopper; changing the amorphous channel layer to be a polysilicon layer by activating the implanted impurities; and forming a source electrode and a drain electrode by depositing a metal layer on the resultant and by patterning the metal layer in some portions thereof.
According to the present invention, since at least two gate electrodes are formed in the POLY-TFT, the channel length is increased. Therefore, the drain electric field is decreased and the leakage current is also decreased in the off-state. Further, although the channel length is increased, the decrease in the ON current of the thin film transistor is prevented by forming the auxiliary junction region between the source and drain regions.
REFERENCES:
patent: 4003868 (1977-01-01), Smith et al.
patent: 4678281 (1987-07-01), Bauer
patent: 4945067 (1990-07-01), Huang
patent: 5010027 (1991-04-01), Possin et al.
patent: 5057889 (1991-10-01), Yamada et al.
patent: 5066106 (1991-11-01), Sakamoto et al.
patent: 5191453 (1993-03-01), Okumura
patent: 5371025 (1994-12-01), Sung
patent: 5581382 (1996-12-01), Kim
patent: 5602047 (1997-02-01), Tsai et al.
patent: 5771083 (1998-06-01), Fujihara et al.
patent: 5817548 (1998-10-01), Noguchi et al.
patent: 5834071 (1998-11-01), Lin
patent: 5877514 (1999-03-01), Seo
patent: 6046479 (2000-04-01), Young et al.
patent: 553137 (1993-03-01), None
patent: 572995 (1993-03-01), None
Cho Dae Han
Lee Kyung Ha
Chaudhuri Olik
Hyundai Display Technology Inc.
Pizarro-Crespo Marcos D.
Selitto Behr & Kim
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