Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1995-10-31
2001-02-27
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S626000, C438S655000, C438S657000
Reexamination Certificate
active
06194296
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor structure which includes polycide. The invention has broad applicability to the fabrication of various semiconductor structures.
BACKGROUND OF THE INVENTION
Polycide refers to a structure which includes a layer of doped polycrystalline silicon (polysilicon) and an overlying metal silicide layer. Polycide is used, for example, to form gate electrodes in field effect transistors (FETs).
FIG. 1
is a top view of an n-channel FET
100
which includes source region
101
, drain region
102
, polycide gate electrode
103
, and field oxide
107
.
FIG. 2
a
is a cross sectional view of FET
100
along plane
2
a
—
2
a
of FIG.
1
.
FIG. 2
b
is a cross sectional view of FET
100
along plane
2
b
—
2
b
of FIG.
1
.
FIGS. 2
a
and
2
b
also show gate oxide
106
and silicon semiconductor substrate
110
.
Polycide gate electrode
103
is typically fabricated by depositing a layer of polysilicon
103
a
over field oxide
107
and gate oxide
106
, conductively doping polysilicon layer
103
a
, depositing a layer of metal silicide
103
b
over polysilicon layer
103
a
, and performing one or more masking and etching steps. Polycide gate electrode
103
can also be formed by depositing and conductively doping polysilicon layer
103
a
, depositing a metal layer over polysilicon layer
103
a
, and performing a heating step in which part, but not all, of polysilicon layer
103
a
is consumed to form a metal silicide layer over the remaining polysilicon layer.
Polysilicon layer
103
a
provides an appropriate work function to gate electrode
103
and an appropriate threshold voltage to FET
100
according to the work function and the voltage threshold parameters desired. Silicide layer
103
b
provides a low contact resistance with polysilicon layer
103
a
(compared, for example, to an aluminum gate electrode) and reduces the overall sheet resistance of gate electrode
103
.
There are several drawbacks associated with polycide gate electrode
103
. As illustrated in
FIG. 2
b
, silicide layer
103
b
typically has bad step coverage. In the areas where underlying polysilicon layer
103
a
undergoes a change in height, i.e., at portions
111
and
112
, silicide layer
103
b
is deposited to a lesser thickness than the remainder of silicide layer
103
b
. Portions
111
and
112
have a high resistance compared to the rest of silicide layer
103
b
, thereby undesirably increasing the resistance of gate electrode
103
.
Another problem with FET
100
is that topography changes at the surface of the FET structure can cause depth of focus difficulties when performing conventional lithography steps. This loss of resolution requires the use of a wider line size.
A further problem with polycide gate
103
is that silicide layer
103
b
exerts stress on polysilicon layer
103
a
. If this stress becomes large enough, damage to the underlying gate oxide
106
may occur.
Another problem is specific to polycides fabricated by tungsten chemical vapor deposition (CVD). A tungsten fluoride gas (WF
6
) in a silane (SiH
4
) carrier is typically used during the CVD fabrication of tungsten silicide (WSi
x
, where x≧2). Some of the fluorine in the tungsten fluoride gas may be present in the tungsten silicide after the tungsten silicide is deposited. This fluorine can diffuse through the underlying polysilicon layer
103
a
to gate oxide
106
during subsequent thermal cycling, thereby degrading the dielectric properties of gate oxide
106
.
Another problem can occur when etching unwanted portions of a polycide structure. For example, if polycide gate
103
of
FIG. 2
b
is anisotropically etched, undesired spacers, referred to as silicide stringers, may be formed adjacent to step portions
111
and
112
because the vertical thickness of silicide layer
103
b
is too thick to be completely removed at these locations.
FIG. 3
illustrates silicide stringers
121
-
122
. Silicide stringers
121
-
122
can undesirably create leakage paths between gate electrodes. To eliminate silicide stringers
121
-
122
, the silicide etch is sometimes prolonged. However, because the selectivity of the silicide etchant to polysilicon is typically less than 1:1, the silicide etchant will attack the underlying polysilicon layer
103
a
faster than silicide layer
103
b
. Thus, any attempt to prolong the silicide etch to remove silicide stringers
121
-
122
may result in the removal of an excessive amount of polysilicon layer
103
a
. If the prolonged silicide etch extends through polysilicon layer
103
a
, the gate oxide layer
106
may be attacked. The selectivity of the silicide etchant to silicon oxide is typically in the vicinity of 5:1 to 1:1. The silicide etchant can therefore potentially reach and undesirably destroy portions of gate oxide
106
.
It would therefore be desirable to have a structure and method of forming a polycide gate which eliminates or mitigates the above-described shortcomings of prior art polycide structures.
SUMMARY
Accordingly, the present invention provides a planarized polycide structure and a method for making the same. One embodiment includes a semiconductor structure having an irregular upper surface. This irregular upper surface can be caused, for example, by the presence of field oxide surrounding an active region of an FET. A layer of polycrystalline silicon (polysilicon), is located over the irregular upper surface of the semiconductor structure. The polysilicon layer has a substantially flat upper surface. A metal silicide layer having a substantially uniform thickness is located over the flat upper surface of the polysilicon layer, thereby forming a planarized polycide structure. This planarized polycide structure can be used, for example, as a gate electrode in an FET. Because the metal silicide layer is located over the flat upper surface of the polysilicon layer, the problems associated with prior art polycide structures are mitigated.
More specifically, the prior art problems caused by irregularities in the upper surface of the polysilicon layer, namely, poor silicide step coverage, loss of resolution during photolithography and formation of silicide stringers, are eliminated because the metal silicide layer is located over the flat upper surface of the polysilicon layer.
To provide a polysilicon layer having a flat upper surface, the thickness of the polysilicon layer is made larger than the thickness of a conventional polysilicon layer
103
a
(
FIGS. 2
a
-
2
b
). The thicker polysilicon layer advantageously dissipates the stress introduced by the metal silicide layer. In addition, the thicker polysilicon layer makes it less likely that impurities such as fluorine will seep through the polysilicon layer to an underlying gate oxide.
In an alternative embodiment, the planarized polycide structure includes a first polysilicon layer located a semiconductor substrate. The polysilicon layer has an irregular upper surface. A dielectric layer is located over a portion of the upper surface of the polysilicon layer, such that the upper surface of the dielectric layer and the portion of the upper surface of the polysilicon layer which does not underlie the dielectric layer are substantially co-planar. A metal silicide layer is located over the co-planar upper surfaces of the polysilicon layer and the dielectric layer. In one embodiment, a portion of the metal silicide layer contacts a portion of the polysilicon layer. In another embodiment, a second polysilicon layer is located over the co-planar upper surfaces of the polysilicon layer and the dielectric layer, and the metal silicide layer is located over the second polysilicon layer.
The present invention also includes methods for forming polycide over a semiconductor structure having an irregular upper surface. One such method includes the steps of:
(1) forming a first layer of non-monocrystalline silicon over the irregular upper surface of the semiconductor structure,
(2) planarizing the upper surface of the first non-monocrystalline silicon layer, and
(3) forming a met
Bever Hoffman & Harms LLP
Integrated Device Technology Inc.
Quach T. N.
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