Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-03-22
2004-03-02
Kielin, Erik J. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S945000, C438S962000
Reexamination Certificate
active
06699779
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to nanoscale electric devices, and more particularly, to a method for making nanoscale wires and gaps for switches and transistors.
BACKGROUND OF THE INVENTION
Reducing the feature size of integrated circuit components is a continuing goal of semiconductor process designers. In the past, such reductions have led to decreased cost and increased operating speed. Device fabrication depends on techniques that rely on masks to define the boundaries of the transistors and conductors. For example, metal and semiconductor conductor patterns are fabricated by lithography in which masks determine the location and size of the patterns. The conductivity in semiconductors can also be controlled by implanting ions. The areas that are to be implanted are typically defined by an opening in a mask. Similarly, transistors require the selective implantation of ions. Unfortunately, conventional masking techniques are inadequate when nanometer scale components are to be fabricated.
Broadly, it is the object of the present invention to provide a self-assembled masking technique for use in fabricating nanoscale wires and devices in integrated circuits.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention and the accompanying drawings.
SUMMARY OF THE INVENTION
The present invention is a method for forming first and second linear structures of a first composition that meet at right angles, there being a gap at the point at which the structures meet. The linear structures are constructed on an etchable crystalline layer having the first composition. First and second self-aligned nanowires of a second composition are grown on a surface of the etchable crystalline layer, the first nanowire growing at right angles to the second nanowire. The first nanowire is separated from the second nanowire by a gap of less than 10 nm at their closest point. Portions of the etchable layer that are not under the first and second nanowires are then etched using the first and second nanowires as a mask thereby forming the first and second linear structures of the first composition. The nanowires are grown by depositing a material of the second composition which forms crystals on the surface that have an asymmetric lattice mismatch with respect to the crystalline surface. The linear structures so formed are well suited for the fabrication of nanoscale transistors having a first elongated doped semiconductor wire having a width between 1-100 nm on an insulative substrate. A second wire at right angles to the first ridge acts as the gate of the transistor. The two wires are separated by a gap of between 0.4 and 10 nm at their closest point. By filling the gaps with appropriate materials, the wires and gaps can also function as a nanoscale memory switch and a transistor.
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Chen Yong
Williams R. Stanley
Hewlett--Packard Development Company, L.P.
Kielin Erik J.
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