Method for making micro-mechanical semiconductor accelerometer

Semiconductor device manufacturing: process – Making device or circuit responsive to nonelectrical signal – Physical stress responsive

Reexamination Certificate

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C073S514070, C073S03200R

Reexamination Certificate

active

06294400

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to accelerometers. More particularly, the invention pertains to a high-precision, micro-mechanical semiconductor accelerometer of the differential-capacitor type.
2. Description of the Prior Art
Precision micro-mechanical accelerometers have wide application in the fields of inertial navigation and guidance, both with respect to long-range, re-usable vehicles, such as aircraft, and to relatively short-range, one-use vehicles, such as munitions. Such inertial sensors are employed both to measure linear accelerations and to measure vehicular angular rates within an inertial navigation system when employed in Coriolis-based systems. A representative type of system for measuring both linear accelerations and rotation rates with reference to a set of three orthogonal axes is the multi-sensor as taught, for example in United States patents (property of the assignee herein) U.S. Pat. No. 4,996,877, entitled “Three Axis Inertial Measurement Unit With Counterbalanced Mechanical Oscillator”; U.S. Pat. No. 5,007,289, entitled “Three Axis Inertial Measurement Unit With Counterbalanced, Low Inertia Mechanical Oscillator”; and U.S. Pat. No. 5,065,627 entitled “Three Axis Inertial Measurement Unit With Counterbalanced, Low Inertia Mechanical Oscillator”.
Precision micro-mechanical accelerometers can take several functional forms including the so-called differential-capacitor type. In general, this type employs a central plate or proofmass disposed between two fixed outer plates and moveable at a flexure in response to an acceleration force along its sensitive axis. In an open-loop system, the two values of capacitance defined between the central plate and respective ones of the outer plates are differenced, with the change in capacitance resulting from a displacement of the central plate being picked off by electrodes and employed as the measure of the acceleration force.
In a closed loop system, measured changes in the differential capacitance are fed back in the form of electrostatic field forces applied to the respective plates of the two capacitors to restore and maintain the central plate precisely between the two outer plates. The electrostatic force required to restore and maintain the central plate at the null condition is the measure of the inertial force acting on the plate. Such accelerometers, when used in conjunction with an appropriately-sensitive capacitive measurement system, are capable of detecting and measuring extremely minute accelerations, (approximately 1 &mgr;G). An example of such a system employing charge control forcing and rate multiplier outputs is taught in U.S. Pat. No. 5,142,921 entitled “Force Balance Instrument with Electrostatic Charge Control”, property of the assignee herein.
Accelerometer arrangements in which a silicon proofmass is sandwiched between a pair of opposed glass plates with plated-on metallic electrodes have experienced inefficiency due to the differing coefficients of thermal expansion of the glass plates and the silicon disk sandwiched therebetween. Such thermal incompatibility can produce warping with temperature changes, resulting in excessive bias and scale factor temperature sensitivities. An additional problem encountered with accelerometers employing glass plates is that mobile ion redistribution with thermal cycling causes non-repeatability of bias and scale factor.
U.S. Pat. No. 5,614,742 ('742 Patent) entitled “Micromechanical Accelerometer With Plate-Like Semiconductor Wafers” (also property of the assignee herein, the teachings of which are hereby incorporated by reference) teaches an all-silicon, precision micro-mechanical accelerometer that substantially overcomes the aforesaid problems. The accelerometer of the patent comprises an assembly of five anisotropiocally-etched silicon wafers (each formed by a conventional wet process) bonded to one another to form a hermetically-sealed assembly. By employing a structure entirely of silicon layers coated with thin oxide layers, the thermal coefficient mismatches of the prior art are substantially overcome. As a result, the device of the '742 Patent is able to withstand a wider range of temperature variation with reduced temperature sensitivity and improved repeatability and stability.
While the above-described device provides quite satisfactory results in terms of both tactical performance and cost, the patented assembly entails the etching of five separate wafers followed by their subsequent registration and bonding. The etching process for defining the electrodes and their screening frames employs conventional etching solutions such as potassium hydroxide (KOH). Such solutions can, under certain circumstances, produce alkaline ions that penetrate into and contaminate the silicon oxide layers, degrading accelerometer performance. The anisotropic nature of the etching process, which proceeds along the crystallographic planes of the silicon layers defines sloped, rather than straight, sidewalls. In the assembled accelerometer, such sloped edges result in regions of “non-forcing mass” where edge portions are spaced too far from the electrodes to be interactively responsive to the voltages nominally applied. Thus, higher voltages must be applied to overcome the extra mass. This situation occurs whether the electrodes act as forcers (as in the case of a closed-loop system), or signal pick-offs (as in the case of both open- and closed-loop systems).
SUMMARY OF THE INVENTION
The preceding and other shortcomings of the prior art are addressed by the present invention which provides, a method for producing a semiconductor accelerometer of the differential capacitor type. Such method includes the step of selecting a semiconductor proofmass wafer and a pair of SOI wafers of the type that have an oxide layer between semiconductor handle and device layers. Such method includes the step of fixing a first thickness of dielectric material on the opposite sides of each SOI wafer and fixing a second thickness of dielectric material on opposite sides of the proofmass layer.
The device layer and the first thickness of dielectric material overlying the device layer of each SOI wafer is etched through to the underlying oxide layer to define on the device layer an associated central electrode in a continuous, marginal frame around the electrode. A proofmass wafer and the second thickness of dielectric material on the opposite sides thereof are etched to define within that wafer a central proofmass having opposite faces, a continuous, marginal frame around the proofmass and a flexible hinge connecting the proofmass to the frame.
The proofmass wafer is assembled between opposed ones of the SOI wafers so that the frames of the wafers are in alignment, the proofmass is centered between and spaced apart from respective, opposed ones of the electrodes by distance equal to the sum of the first and second thicknesses of dielectric material and the proofmass is articulated to rotate between the electrodes and the hinge. Each SOI wafer is bonded to a respective one of the opposed sides of the proofmass wafer so that a respective one of the first thickness of dielectric material on the frames around the electrodes is fused to a respective one of the second thicknesses of dielectric material on the opposed sides of the frame around the proofmass to form a hermetically sealed assembly.


REFERENCES:
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patent: 5007289 (1991-04-01), Stewart et al.
patent: 5065627 (1991-11-01), Stewart et al.
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patent: 5614742 (1997-03-01), Gessner et al.
patent: 5623099 (1997-04-01), Schuster et al.
patent: 5905203 (1999-05-01), Flach et al.

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