Fishing – trapping – and vermin destroying
Patent
1996-03-28
1997-12-30
Bowers, Jr., Charles L.
Fishing, trapping, and vermin destroying
437231, 437228, 437DIG978, H01L 2144
Patent
active
057029822
ABSTRACT:
A method for making metal interconnections and buried metal plug structures for multilevel interconnections on semiconductor integrated circuits was achieved. The method utilizes a single patterned photoresist layer for etching trenches in an insulating layer, while at the same time protecting the device contact areas in the contact openings from being etched, thereby reducing process complexity and manufacturing cost. After the trenches are formed, the patterned photoresist layer and the photoresist in the contact openings is removed by plasma ashing, and a metal layer is deposited and etched back or chem/mech polished to form concurrently the metal interconnections and the buried metal plug contacts. The surface of the metal interconnections is coplanar with the insulating surface, thereby allowing the process to be repeated several times to complete the necessary multilevel of metal wiring needed to wire-up the integrated circuits while maintaining a planar surface.
REFERENCES:
patent: 5173442 (1992-12-01), Carey
patent: 5284799 (1994-02-01), Sato
patent: 5409862 (1995-04-01), Wada et al.
K. Ueno et al, "A Half-Micron Pitch Cu Interconnection Technology" 1995 Symposium on VLSI Technology Digest , pp. 27-28.
Hsu Jung-Hsien
Lee Chung-Kuang
Tseng Pin-Nan
Ackerman Stephen B.
Bowers Jr. Charles L.
Gurley Lynne A.
Saile George O.
Taiwan Semiconductor Manufacturing Company , Ltd.
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