Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-12-27
2008-10-14
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C430S004000
Reexamination Certificate
active
07437702
ABSTRACT:
A method for making a mask in a process of fabricating a semiconductor device is disclosed, in which one database is classified into an SRAM block and a random logic block so that OPC is separately performed for the SRAM block and the random logic block, thereby improving performance of the OPC. The method includes dividing an input database into an SRAM block and a random logic block, respectively performing optical proximity correction (OPC) for the SRAM block and the random logic block, and combining the SRAM block to the random logic block.
REFERENCES:
patent: 6525969 (2003-02-01), Kurihara et al.
patent: 6977834 (2005-12-01), Onizawa et al.
patent: 7207017 (2007-04-01), Tabery et al.
patent: 7275227 (2007-09-01), Ying
Dongbuanam Semiconductor Inc.
McKenna Long & Aldridge LLP
Siek Vuthe
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