Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
2002-02-01
2003-07-29
Whitehead, Jr., Carl (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S517000, C257S288000, C257S369000
Reexamination Certificate
active
06600205
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
This invention is in the field of integrated circuits, and is more specifically directed to the construction of field-effect transistors used in such circuits.
A continuing trend in the field of electronic integrated circuits is the reduction in transistor feature size. These smaller feature sizes enable a higher level of functionality for the integrated circuit, and also significantly reduce the manufacturing cost of the circuit. The manufacturing cost is reduced not only by increasing the number of integrated circuit dies that may be fabricated on a single wafer (and thus for substantially the same cost), but also by increasing the theoretical yield of the wafer for a given defect density by reducing the area affected by a single “killing” defect. Additionally, the performance of the integrated circuit generally improves along with the faster switching times provided by smaller transistors.
The reduction in transistor feature sizes has necessitated, in many instances, a reduction in the operating voltages applied to the integrated circuit, because many of the device breakdown voltages are lower for smaller devices. For example, a smaller channel length in a metal-oxide semiconductor (MOS) transistor generally translates into a lower source-to-drain breakdown voltage. Additionally, reduction in lateral transistor feature sizes, such as channel lengths and electrode widths, generally also necessitates reduced junction depths and other vertical features.
Some integrated circuit applications still require high voltage operation, however. For example, the use of integrated circuits in motor control and automotive applications may require high-voltage output signals, because of the load requirements of such devices. Additionally, some environments may also require integrated circuits to be able to withstand high bias voltages. Accordingly, modern integrated circuits utilizing extremely small active devices and transistors are not directly suitable for these applications.
In the past, separate “power” integrated circuits were used in combination with low-voltage high-performance integrated circuits in high-voltage applications. In this way, the high-performance integrated circuits could control the power ICs, which in turn would sink and source the high voltage or high current signals required by the application. Of course, for purposes of cost reduction, reduced form factor, and performance, it is desirable to integrate as much functionality as possible into the same integrated circuit. As a result, many modem integrated circuits include both high-performance (or “low-voltage”) and high-voltage transistors.
However, the manufacturing processes required for integrating both high-performance and high-voltage transistors into the same integrated circuit can become quite complicated. It has been observed, in connection with the present invention, that the differences in construction between conventional low-voltage and high-voltage transistors do not permit optimization of both transistors in the same process. These differences are particularly dramatic in the formation of the wells into which the transistors are formed. As a result, conventional manufacturing flows utilize separate processes for the fabrication of low-voltage and high-voltage transistors.
Referring now to
FIGS. 1
a
and
1
b
, the construction of a conventional high-performance, or “low-voltage”, p-channel MOS transistor is illustrated in plan and cross-sectional views, respectively. In this example, the transistor is formed at a surface of p-type substrate
2
, on which p-type epitaxial layer
3
is formed in the conventional manner. The transistor is formed into n-well
4
, which serves as the body region of the MOS transistor. Field oxide structures
5
, which may be either conventional LOCOS thermal silicon oxide or silicon oxide deposited into recesses etched into the surface, define the active regions of the device. Polysilicon gate electrode
10
is disposed over a selected location of this active region, and p+ diffused regions
6
are formed into n-well
4
at locations not covered by field oxide structure
5
and gate electrode
10
; as a result, p-type source and drain regions of the transistor are formed in a self-aligned manner relative to gate electrode
10
. Sidewall filaments may be provided on the sides of gate electrode, if desired, to facilitate later silicidation of the structure and to permit the formation of graded source-drain junctions (typically more appropriate for n-channel devices). Following the deposition of multilevel insulator
7
(which is not shown in
FIG. 1
a
to permit viewing of the structure) and the etching of contact openings through this film, metal conductors
8
may be formed in the conventional manner to make contact to the desired elements of the transistor. In this example, metal electrodes
8
s
and
8
d
make contact to the source and drain of the transistor, respectively, while metal electrode
8
bg
makes a “back-gate” contact (also referred to as a “body” contact) to well
4
via n+ diffused region
9
, so that the body region of the device may be biased to a desired voltage.
Several features of the transistor of
FIGS. 1
a
and
1
b
are specific to low-voltage, high-performance, devices. Generally, n-well
4
will be relatively shallow, and relatively heavily doped (although not as heavily doped as source-drain regions
6
). For example, in a conventional sub-micron process, n-well
4
may be on the order of two microns deep into epitaxial layer
3
, and may have a doping concentration of on the order of 3×10
16
cm
−3
resulting in a sheet resistance of on the order of 850 &OHgr;/square. By making n-well
4
to be relatively shallow and heavily-doped, short-channel-length transistors formed in well
4
can have relatively high gain values of g
m
(or k′), and this will have quite high performance. In addition, this construction permits excellent transistor matching behavior, as is necessary for precise applications such as current mirror circuits.
However, the heavy doping of n-well
4
necessary for high transistor gain results in relatively low breakdown voltages. For example, the transistor of
FIGS. 1
a
and
1
b
can have a source-drain breakdown voltage of on the order of five volts or lower. Additionally, the heavy doping of n-well
4
can limit the junction breakdown voltage at its interface with epitaxial layer
3
to as low as 25 volts or lower. While these breakdown voltages are well-suited for many high-speed circuit applications, some motor control and automotive applications cannot be implemented using such devices.
FIGS. 2
a
and
2
b
illustrate the construction of a high-voltage transistor, for which the breakdown voltages are significantly higher than in the case of the low-voltage transistor described above. This high-voltage transistor has many common features with the transistor of
FIGS. 1
a
and
1
b
, including p+ diffused regions
16
and n+ diffused region
17
, the locations of which are defined by field oxide structures
5
and gate electrode
18
. Gate electrode
18
is significantly wider (from source-to-drain) than gate electrode
10
in the low-voltage transistor, providing a longer channel length and thus a higher source-drain breakdown voltage (e.g., on the order of ten to fifteen volts). This longer channel length is acceptable for this device, considering that transistor gain is not a major concern for high-voltage transistors. Metal electrodes
8
bg
,
8
s
,
8
d
are provided to make contact to the body node, source, and drain respectively.
The high-voltage transistor is also similarly formed into substrate
2
and epitaxial layer
3
. However, n-well
14
is significantly more lightly doped, and also deeper, than the corresponding n-well
4
in the low-voltage device. For example, n-well
14
may have a doping concentration of on the order of 4×10
15
cm
−3
, resultin
Carpenter, Jr. John H.
Devore Joseph A.
Tanaka Toru
Huynh Yennhu B.
Jr. Carl Whitehead
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