Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-10-29
2001-09-25
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S636000, C438S671000, C438S688000
Reexamination Certificate
active
06294465
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of semiconductors, and, more particularly, to a method for making integrated circuits on a semiconductor wafer.
BACKGROUND OF THE INVENTION
Integrated circuits are widely used in electronic devices, such as computers, cellular telephones, entertainment systems, etc. A typical integrated circuit includes a semiconductor substrate with a plurality of active regions formed therein. These active regions may be interconnected by various conductive or metal lines formed in layers on the substrate. Accordingly, an integrated circuit may include millions of transistors, for example.
As the densities of integrated circuits are continually increased, each feature, such as the width of a metal line, or the width of a polygate oxide layer, is continually reduced. Smaller features permit faster operation, less power consumption and more complicated functions to be performed. Such features are typically defined by selective exposure of a photoresist layer on a semiconductor wafer to a pattern imaged from a mask or reticle in a process generally known as optical lithography or photolithography. The exposed photoresist layer portions may be made etch resistant upon exposure to the image, for example. The non-exposed portions may then be removed leaving the desired photoresist pattern. The chemistry of the photoresist may also provide that exposed portions are etched and non-exposed portions remain. The remaining resist portions are then typically used to provide elective etching of the underlying integrated circuit portions.
The resolution, and hence minimum feature size, is related to the wavelength of light used in the photolithography. The so-called Rayleigh resolution criteria will soon define the limit of physics for imaging the ever-shrinking feature size in integrated circuit manufacturing. Continuing developments have allowed optical lithography to keep pace with the demand for decreasing feature sizes. As noted in the IEEE Spectrum article “Ultralight Lithography” appearing at pp. 35-40, in July 1999, the lifetime of a given lithography generation is modified until a complete change to a next generation technology is made. In other words, various corrective measures are taken to help pattern smaller features, and which is limited by the wavelength of light used. Typical corrective techniques include optical proximity correction (OPC) and the use of phase-shift masks. However, such phase-shift masks and OPC masks can be relatively expensive.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to provide a method for making integrated circuits having smaller feature sizes.
This and other objects, features and advantages in accordance with the present invention are provided by a method for making an integrated circuit which relies upon an interaction between the photoresist, the developer, and an aluminum layer which is at least partly uncovered on the semiconductor wafer.
The method preferably includes the steps of forming an aluminum layer adjacent a semiconductor wafer, forming a photoresist layer adjacent the aluminum layer with at least a portion of the aluminum layer being uncovered, and exposing the photoresist layer to a pattern image. Moreover, the method also preferably includes developing the exposed photoresist layer using a developer and stripping away undeveloped photoresist portions to define a mask including mask features having reduced widths than would otherwise occur adjacent the aluminum layer. The reduced widths are based upon an interaction between the photoresist, the developer and the aluminum. The method may also include etching the aluminum layer using the mask having the reduced widths to thereby define circuit features having a smaller critical dimension than would otherwise be produced.
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patent: 5397433 (1995-03-01), Gabriel
patent: 5525542 (1996-06-01), Maniar et al.
patent: 5846878 (1998-12-01), Horiba
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IEEE SpectrumJul. 1999, vol. 36, No. 7. Article: “Ultralight Lithography”, pp. 35-40. (W/copies of tables, figures, etc.).
Gil Carlos De Miguel
Hernandez Jose Luis
Morena Ines Vincueria
Agere Systems Guardian Corp.
Alan, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
Brophy Jamie L.
Meier Stephen D.
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