Method for making hyperfrequency transistor

Details Method for making hyperfrequency transistor Method for making hyperfrequency transistor

1999-12-29

2002-06-11

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Having heterojunction

Reexamination Certificate

active

06403437

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a bipolar transistor with a semi-aligned structure and the method for producing such a transistor. The invention particularly relates to the production of hyperfrequency bipolar transistors. The invention therefore relates to the field of microelectronics on silicon, particularly for producing bipolar integrated circuits and BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuits.
The invention has applications in the production of logic circuits, analog circuits and particularly radiofrequency circuits.
BACKGROUND ART
Transistors said to have an auto-aligned double-polysilicon structure are known in the art. Given their outstanding operating speed, these transistors offer the highest performance levels available today. Their high operating speed results from the auto-aligning character of the component parts of these transistors that also ensures the accuracy of their construction. Moreover, the auto-aligned structure enables transistors to be obtained that are small and perfectly suited to producing integrated circuits. Documents (1) and (2) may be referred to for further information concerning this subject. The references of the documents are given at the end of the present description.
The structure and manufacture of a bipolar transistor of the type mentioned above are briefly described with reference to
FIGS. 1
to
3
attached.
A transistor formation zone
102
is first defined on a silicon substrate
100
by creating thick zones of silicon oxide
104
using the “LOCOS” (Local Oxidation of Silicon) technique on the surface of the substrate. Next a first layer of polycrystalline silicon
106
doped with boron and an insulating layer
108
of silicon oxide or silicon nitride are deposited successively on the surface of the silicon substrate.
Reference
110
in
FIG. 1
indicates an N
+
layer that is doped with arsenic and embedded in substrate
100
. This layer constitutes the transistor collector that is subsequently created.
An etching mask
112
is formed on insulating layer
108
. The mask includes an aperture that defines the subsequent position of the transistor emitter.
FIG. 2
shows the next stage in which a window
114
is made through polycrystalline silicon layer
106
and insulating layer
108
in order to reveal an area of silicon substrate
100
. The position of the window is determined by the aperture in mask
112
on insulating layer
108
.
Window
114
is made using an anisotropic reactive ionic etching technique. The depth of the etching is adjusted by varying the length of etching time.
However, when the etching time is insufficient a section of the doped polycrystalline silicon layer
106
remains at the bottom of window
114
. Under these circumstances the transistor base that will be made later lies in this section of the polycrystalline silicon layer and the resulting transistor is unusable because it has zero gain.
In order to avoid this situation sufficient etching time is chosen to ensure the polycrystalline silicon is completely eliminated from the window. However, in this event the silicon from the substrate is also attacked and part of window
114
extends into substrate
100
. This phenomenon, shown in
FIG. 2
, is referred to as “over-etching” in the text that follows.
The following stage shown in
FIG. 3
mainly concerns production of the transistor emitter in window
114
. The emitter comprises an N
+
-type polycrystalline silicon layer
116
that is doped with arsenic. It is electrically insulated from the sides of window
114
by a thin layer of thermal oxide
118
and lateral spacers
120
that cover the sides. The emitter is also insulated from the first polycrystalline silicon layer
106
by insulating layer
108
.
It should be noted that boron ions are embedded in substrate
100
via window
114
before polycrystalline silicon layer
116
is formed on the emitter. This embedding enables a base area, called an intrinsic base, to be created in the substrate. This area is referred to as
122
in FIG.
3
.
The thermal treatment used to create thermal oxide layer
118
, or indeed any other thermal treatment used after the emitter has been created, causes doping impurities to be diffused both from the first polycrystalline silicon layer
106
and the polycrystalline silicon layer
116
constituting the emitter into the silicon substrate.
The impurities, particularly boron, being diffused into the substrate from the first polycrystalline silicon layer
106
enable doped areas to be formed that are called “extrinsic bases” in the text that follows. These areas are referred to as
124
in FIG.
3
. Arsenic also being diffused into the substrate
100
from the first polycrystalline silicon layer
116
extends the emitter with an emitter area that is in contact with intrinsic base
122
. The emitter area diffused in the substrate is referred to as
126
in FIG.
3
.
It may be noted that the extrinsic and intrinsic base areas in
FIG. 3
are slightly overlapping. Overlapping is necessary to ensure electrical continuity between extrinsic base
124
and intrinsic base
122
and to enable said intrinsic base to be addressed. A base contact point (not shown in
FIG. 3
) is provided on the first layer of doped polycrystalline silicon that is in contact with extrinsic base
124
.
The extrinsic base
124
area and the emitter area both have high levels of doping. Consequently, in order to avoid the risk of electrical leaks from the transistor it is essential for there to be sufficient distance between these areas.
The method for manufacturing bipolar transistors described above and the transistors obtained using the method have a certain number of drawbacks that have a negative influence on performance levels and on the production output of integrated circuits that include such transistors.
When the over-etching of window
114
(
FIG. 2
) is very deep the diffused area that constitutes the extrinsic base no longer extends as far as the section of the substrate under the emitter. There is then the risk of the electrical contact between the extrinsic and intrinsic bases being eliminated. In this event the intrinsic base remains without electrical access. Furthermore, a high level of over-etching reduces the distance between intrinsic base
122
and the embedded collector layer
110
(FIG.
3
). The lack of distance reduces the resistance voltage between the base and the collector and channeling or avalanche breakdown could occur in the transistor.
Etching of window
114
and over-etching in the silicon of the substrate can also induce crystallographic defects on the emitter-base interface. These defects lead to current leakage from the emitter-base junction that affects the current gain from the transistor. Furthermore, the anisotropic character of the etching of window
114
causes roughness on the emitter-base interface. The roughness affects the result of the chemical treatments to which the substrate is subjected when the transistor is manufactured. For example, a negative occurrence may arise concerning the oxidation speed or the cleaning quality between the various production stages. It is impossible to control the effects caused by roughness.
Therefore the auto-aligning structures described above mainly pose the problem of over-etching the emitter window. In order to avoid major over-etching it is necessary for the polycrystalline silicon etching to be accurately controlled which often proves difficult if production is on an industrial scale.
Another production method called “semi-auto-aligning” is also known. The method facilitates the manufacture of transistors while avoiding over-etching of the substrate and the above-mentioned drawbacks. The method is described below with reference to
FIGS. 4
to
6
.
Part of the preceding description is not repeated given the great similarity between the structures shown in
FIGS. 4
to
6
and those in
FIGS. 1
to
3
. They may, however, be referred to for clearer understanding of the drawings. Furthermore, to simplify the drawi

Affiliated with

Also associated with

Rating

Method for making hyperfrequency transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for making hyperfrequency transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making hyperfrequency transistor will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2919602