Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-04
2001-08-14
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S706000, C438S710000, C438S712000, C438S239000, C438S240000, C438S253000
Reexamination Certificate
active
06274471
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more specifically to a method for making high-aspect-ratio contact openings concurrently to a patterned polycide layer having a Si
3
N
4
hard mask and to the shallow diffused regions on a semiconductor substrate with-out damaging the shallow diffused junctions on the substrate.
(2) Description of the Prior Art
The dramatic increase in circuit density on semi-conductor substrates in recent years is the result of down-scaling of the individual semiconductor devices, such as FETs, built in and on the semiconductor substrate. This downscaling has also resulted in a decrease in the pitch (linewidth+spacing) of patterned electrical conducting layers used as interconnections to wire up these devices. Typically the FET gate electrodes and local interconnections are made from a first polysilicon layer (or polycide layer), with a Si
3
N
4
cap (hard mask) layer, that is patterned. A planar insulating layer, referred to as an interlevel-dielectric (ILD) layer, is then deposited to electrically insulate the FETs from the next level of interconnections. Unfortunately, as the minimum feature sizes decrease to submicrometer dimensions (e.g., less than 0.25 um) the contact openings that are etched in the ILD layer to the FET source/drain areas and are concurrently etched to the polycide interconnections are quite small and can have high aspect ratios (opening height/width) exceeding 9, which are difficult to etch. Another process problem also occurs when these semiconductor devices are scaled down. The junction depth of the FET source/drain diffused areas is also scaled down to minimize short-channel effects. For example, the junction depth is now typically less than 0.1 um, and therefore the source/drain areas are susceptible to over-etch damage when the contact openings are concurrently etched to the polycide local interconnections.
To better appreciate this problem, a schematic cross-sectional view of a portion of an integrated circuit is depicted by the drawing in
FIG. 1
using a conventional process. Typically a silicon substrate
10
is used in which a field oxide
12
is formed to electrically isolate the device areas. After growing a thin gate oxide
14
on the device areas, a polycide layer is deposited made up of a conductively doped polysilicon layer
16
and a silicide layer
18
. A silicon nitride (Si
3
N
4
) hard-mask layer
20
is deposited and layers
20
,
18
, and
16
are patterned to form the FET gate electrodes
2
over the device areas and concurrently to form the interconnections
4
over the field oxide
12
. Typically for narrow channel FETs, to minimize short-channel effects, lightly doped drains
17
(N
−
) are formed, for example by implanting, and then sidewall spacers
22
are formed by depositing a conformal Si
3
N
4
layer and anisotropically etching back. The source/drain contact areas
19
(N
+
) are formed using a second ion implantation to complete the FETs. The FETs are then electrically insulated from the next level of interconnections with an insulating layer
24
, such as silicon oxide (SiO
2
), that is planarized. Contact openings
6
are then etched in layer
24
to the source/drain areas
19
(N
+
) and concurrently to the polycide lines
4
for the next level of electrical interconnections. Unfortunately, because of the closely spaced devices and relatively thick insulating layer
24
, the openings
6
are small (about 0.20 um in width) and have high aspect ratios (HAR), which are difficult to reliably etch open. Further, because of hard mask
20
it is difficult to etch open the contacts to the silicide layer
18
without overetching and damaging the diffused junctions in area A in the device areas, as depicted in FIG.
1
.
Several methods for making borderless contacts include U. S. Pat. No. 5,792,703 to Bronner et al. in which a first set of contacts is made self aligned and borderless to FET gate electrodes, and a second set of contacts is made with borders. Barber et al., U.S. Pat. No. 4,966,870, teach a method for making borderless contacts through a borophosphosilicate glass (BPSG) and an underlying Si
3
N
4
layer using two different gas mixtures for plasma etching. Huang et al. in U.S. Pat. No. 5,674,781 describe a method for forming landing pads that also form concurrently local interconnections and borderless contacts for deep sub-half-micrometer integrated circuit applications. Another method is described in U.S. Pat. No. 5,759,867 to Armocost et al. in which disposable corner etch-stop spacers are used to form borderless contacts. In U.S. Pat. No. 5,710,078 to Tseng, a method is taught for making contacts to polycide structures with reduced contact resistance. However, none of the above references describes forming contacts concurrently to polycide structures and to shallow diffused areas on a substrate.
Therefore, there is still a strong need in the semiconductor industry for etching very small electrical contact openings that have closely spaced patterned polycide layers on ULSI circuits, and concurrently etching to a substrate without damaging the shallow diffused junction areas on the substrate.
SUMMARY OF THE INVENTION
Accordingly, it is a principal object of this invention to provide contact openings, having high aspect ratios, through an insulating layer to shallow diffused junctions in the source/drain areas in a silicon substrate and concurrently etching openings to a patterned polycide layer while preventing plasma-etch damage to the diffused junctions of the source/drain areas.
A further objective of this invention is to use a bottom anti-reflective coating (BARC) to protect the source/drain areas during removal of a hard mask over a patterned polycide layer prior to etching these high-aspect-ratio contact openings.
Still another object of this invention is to provide a method for more reliably and repeatable etching open the contact openings to the polycide without over-etching and damaging the shallow diffused junctions (source/drain areas) on the substrate.
Now in accordance with the objectives of this invention, a method is described for forming very small contact openings having high aspect ratios to a patterned polycide layer and concurrently etching contact openings to diffused areas such as source/drain areas on a substrate without overetching and damaging the diffused areas having shallow junctions. The method is particularly useful for high-density integrated circuits such as embedded DRAMs.
The method begins by providing a semiconductor substrate, such as a P-doped single crystal silicon substrate having device areas surrounded and isolated from each other by Field OXide (FOX) areas. A polycide layer composed of a conductively doped polysilicon and an upper refractory metal silicide layer is deposited. A hard-mask layer, such as Si
3
N
4
, is deposited on the polycide layer. The hard-mask layer and the polycide layer are patterned to form FET gate electrodes over the device areas, and the polycide layer is concurrently patterned to form local interconnections over the FOX areas. A first ion implantation is used to form lightly doped source/drain areas adjacent to the FET gate electrodes. A conformal Si
3
N
4
layer is deposited and etched back to form sidewalls on the gate electrodes. A second ion implantation is then used to form source/drain contact areas. Next, by the method of this invention, an anti-reflective coating layer is deposited on the substrate, which is used to protect the source/drain areas from overetching at a later process step. The anti-reflective coating layer is preferably a polymer that is impervious to organic solvents and/or aqueous developers that are used in developing photoresist. For the purpose of this invention, the anti-reflective coating does not contain any photo-sensitive components that would be chemically removed during exposure and development of photoresist. A photoresist layer is coated on the anti-reflective layer. The photoresis
Ackerman Stephen B.
Berry Renee R
Nelms David
Saile George O.
Taiwan Semiconductor Manufacturing Company
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