Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2005-11-01
2005-11-01
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S132000, C438S237000, C438S257000, C438S593000
Reexamination Certificate
active
06960495
ABSTRACT:
A method for forming a contact in a three dimensional monolithic memory is disclosed. In a preferred embodiment, the method comprises depositing a conductive layer over and in contact with a plurality of antifuses, wherein said antifuses are part of a story of active devices formed above a substrate; patterning and etching said conductive layer and insulating dielectric to form a contact void; and filling the contact void, wherein the conductive layer does not comprise silicon.
REFERENCES:
patent: 5904507 (1999-05-01), Thomas
patent: 5962910 (1999-10-01), Hawley et al.
patent: 6509209 (2003-01-01), Shroff et al.
patent: 6534403 (2003-03-01), Cleeves
patent: 2004/0002186 (2004-01-01), Vyvoda et al.
Herner S. Brad
Vyvoda Michael
Le Dung A.
Matrix Semiconductor, Inc
Matrix Semiconductor, Inc
Squyres Pamela J.
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