Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1998-09-08
2002-06-18
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S303000, C438S586000
Reexamination Certificate
active
06406987
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to ultra large scale integrated (ULSI) circuits on semiconductor substrates, and more particularly relates to a method for forming reliable borderless contacts in the interlevel dielectric (ILD) layer over the active device area/shallow trench isolation interface.
(2) Description of the Prior Art
To continue increasing the circuit density on future Ultra Large Scale Integration (ULSI) circuits, downscaling is required on the semiconductor chips. This downscaling becomes increasingly difficult as the photolithography resolution improves and minimum feature sizes are reduced in the next generation of devices to deep submicrometer dimensions (e.g., 0.25 and 0.18 um). One method of increasing circuit density is to replace the conventional LOCOS (LOCal Oxidation of Silicon) isolation with a Shallow Trench Isolation (STI) that surrounds and electrically isolates the individual device areas on the silicon substrate. Briefly, the STI is formed by anisotropically etching trenches (with little etch bias) and filling the trenches with a chemical-vapor-deposited (CVD) oxide that is then etched back or chemically/mechanically polished (CMP) back to form a planar surface with the substrate. This replaces the LOCOS isolation which is formed by a thermal oxidation, which by its very nature, oxidizes laterally and intrudes on the device area. Another problem that limits the downscaling is the difficulty in making reliable borderless contacts to the device areas that overlap the STI to reduce the design rules (layout). When making the contact openings for the borderless contacts in an overlying ILD layer, overetching of the STI can result in exposing the shallow diffused junction in the substrate at the sidewall of the upper portion of the trench. The borderless contacts formed by a metal plug in the contact openings short the diffused junction to the substrate body destroying the intended circuit function. This borderless contact problem is best depicted in
FIG. 1
, in which a trench
2
containing an STI
12
is formed in a P
−
doped silicon substrate
10
, and an N
+
shallow diffused contact
19
(N
+
) is formed in the substrate top surface. When an ILD layer
22
is deposited and a borderless contact opening
4
is etched, the STI
12
is overetched. A metal contact
24
formed in the opening
4
results in N
+
contact
19
shorting to the substrate
10
across the P/N junction at point A in the trench sidewall.
Several methods of overcoming these problems are depicted in the prior art drawings in
FIGS. 2 through 5
.
FIG. 2
shows a portion of an FET gate electrode
16
with a gate oxide
14
and two STI regions
12
. The STI
12
is formed having portion
12
′ extending above the surface of the substrate
10
. Silicon nitride sidewall spacers
13
are then formed on the sidewalls of portions
12
′ by depositing and etching back a Si
3
N
4
layer. Unfortunately, when the Si
3
N
4
spacers
13
encroach onto the device-areas, as depicted for the STI
12
on the left, the design rules must be relaxed to provide the necessary area for the device, and therefore limits the device packing density. As shown for the STI
12
on the right, if the Si
3
N
4
spacers do not extend over the interface at A, the STI can be overetched when the borderless contact openings are etched, causing electrical shorts between the shallow N
+
doped contacts
19
and the P
−
substrate.
FIG. 3
shows another approach in which the STI
12
is recessed using a wet-etch dip, and a silicon nitride sidewall spacer
13
is formed by depositing and anisotropically etching back. After recessing the STI
12
and before forming the silicon nitride sidewall spacers
13
, a polysilicon layer
16
is deposited and patterned to form gate electrodes
16
and concurrently to form polysilicon protective visors
15
. However, these closely spaced polysilicon visors
15
can result in poor field isolation across the narrow STI
12
between adjacent device areas.
FIG. 4
shows a method in which the STI
12
is recessed and the Si
3
N
4
visors
13
′ are formed when the Si
3
N
4
layer is anisotropically etched back to form the sidewall spacers
13
on the gate electrode
16
. However, in this method the gate oxide at point B under the gate electrode is eroded when the STI
12
is recessed by etching, and undercutting of the STI
12
at regions C during etching can result in peeling of the patterned polysilicon layer
16
′ and can result in thinning of the STI region. A similar method as depicted in
FIG. 4
is described in the paper entitled “A 2.9 um
2
Embedded SRAM Cell with Co-Salicide Direct-Strap Technology for 0.18 um High Performance CMOS Logic” by K. Noda et al. in IEDM 97 of IEEE, pp. 847-850. Finally, a fourth method is shown in FIG.
5
. In this approach a blanket Si
3
N
4
layer is used to protect the interface A when the borderless contact openings are etched. However, the high stress due to the Si
3
N
4
layer can cause dislocation in the substrate and high leakage currents at the N
+
/P
−
junction between the N
+
contact
19
and the P
−
doped silicon substrate.
U.S. Pat. No. 4,981,813 to Bryant et al. describes a method for forming the conventional LOCOS with reduced bird's beak penetration into the active device area using silicon nitride spacers, thereby allowing increased circuit density. U.S. Pat. No. 5,173,444 to Kawamura describes a method similar to Bryant et al., also using silicon nitride sidewall spacers to reduce the bird's beak and increase circuit density. U.S. Pat. No. 5,652,176 to Maniar et al. uses a liner composed of aluminum nitride in the STI trench prior to filling the trench with SiO
2
. When borderless contacts are etched over the source/drain area-STI interface, the aluminum nitride is retained on the sidewall of the trench and prevents shorting between the source/drain contact and P
−
substrate. Fazan et al. in U.S. Pat. No. 5,433,794 teach a method for making a sidewall spacer, composed of an insulating layer such as SiO
2
or Si
3
N
4
, on the sidewall of a raised STI. The insulating spacers overlap the active device regions and are used to reduce high electric fields (corner effect problem) that would cause device leakage currents. Cronin et al. in U.S. Pat. No. 4,944,682 teach a method for forming borderless contacts (self-aligned contacts) to polysilicon gate electrodes, but do not address borderless contacts to STI. U.S. Pat. No. 5,651,857 to Cronin et al. also teaches a method that form borderless contacts (self-aligned contacts) to polysilicon FET gate electrodes, but does not address making borderless contacts over source/drain areas-STI interfaces.
There is still a strong need in the semiconductor industry to provide improved borderless contacts to shallow diffused contact areas, such as FET source/drain areas on substrates, that also overlap STI without causing shorts between the shallow diffused contacts and the substrate.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to provide borderless contacts to improve circuit density.
It is another object of this invention to provide a method for making more reliable borderless contacts that extend over the active device area/shallow trench isolation interface on a silicon substrate.
Still another object of this invention is to provide a silicon nitride visor (protective covering) on the edge of the active device region to prevent electrical shorting between the substrate and the diffused junction when borderless contacts are made.
A further object of this invention is to prevent erosion of the gate oxide when the shallow trench isolation is recessed for forming the visor.
In summary, these objectives are achieved by this invention, which forms reliable borderless contact openings to the silicon substrate that extend over the active device area/shallow trench isolation (STI) interface. More specifically, the method of a first e
Ackerman Stephen B.
Picardat Kevin M.
Saile George O.
Taiwan Semiconductor Manufacturing Company
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