Method for making an ultra thin FDSOI device with improved...

Details Method for making an ultra thin FDSOI device with improved... Method for making an ultra thin FDSOI device with improved...

2005-12-13

2005-12-13

Smith, Bradley K. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S509000, C257S506000

Reexamination Certificate

active

06975014

ABSTRACT:
A method for forming a FDSOI device with channel length less than 50 nm with good short channel control. The gate has a tapered polysilicon spacer and a dielectric spacer. A polysilicon gate feature is formed and dielectric sidewall spacers are formed thereon. The polysilicon gate feature is then etched to form tapered poly features separated by a gap. A gate dielectric is deposited at low temperature, then metal is deposited into the gap to form the metal gate.

REFERENCES:
patent: 6087208 (2000-07-01), Krivokapic et al.
patent: 6319807 (2001-11-01), Yeh et al.

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