Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2006-05-09
2006-05-09
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S164000, C438S264000, C438S962000, C257SE21404
Reexamination Certificate
active
07041539
ABSTRACT:
A method produces a microstructure comprising an island of material confined between two electrodes forming barriers, the island (30) of material having lateral flanks running parallel to and lateral flanks running perpendicular to the barriers, wherein the lateral flanks of the island are defined by etching of at least one layer (16), called the template layer, and the barriers are formed by damascening. The method includes (a) a first etching of the template layer using a first etching mask having at least one filiform part, and (b) a second etching of the template layer, subsequent to the first etching, using a second etching mask also having at least one filiform part, oriented in a direction forming a non-zero angle with a direction of orientation of the filiform part of the first mask, in the vicinity of the site of formation of the island.
REFERENCES:
patent: 5710051 (1998-01-01), Park et al.
patent: 5844279 (1998-12-01), Tanamoto et al.
patent: 5972744 (1999-10-01), Morimoto et al.
patent: 6042998 (2000-03-01), Brueck et al.
patent: 6091076 (2000-07-01), Deleonibus
patent: 6198113 (2001-03-01), Grupp
patent: 6204517 (2001-03-01), Wu
patent: 6414333 (2002-07-01), Lee et al.
patent: 6441392 (2002-08-01), Gautier et al.
patent: 6472705 (2002-10-01), Bethune et al.
patent: 6527968 (2003-03-01), Wang et al.
patent: 0 844 671 (1998-05-01), None
patent: 2 762 931 (1998-11-01), None
Fujishima et al, “Proposal of a Schottky-Barrier SET Aiming at a Future Integrated Device” IEICE Transactions on Electronics, Institute of Electronics Information and Comm. Eng., Tokyo, JP vol. E80, No. 7, Jul. 7, 1997, pp 881-885.
A. Groshev et al, “Charging Effects of a Single Quantum Level in a Box” Phys. Rev. Lett., vol 66, No. 8, pp. 1082-1085 (1991).
Futatsugi et al., “Silicon Single-Electron Memory Using Ultra-Small Floating Gate,” Fujitsu Sci. Tech. J. 34, Dec. 2, 1998, pp. 142-152.
Hiramoto et al., “Quantum Energy and Charging Energy in Point Contact MOSFETs Acting as Single Electron Transistors,” Superlattices and Microstructures, vol. 25, No. 1/2, 1999, pp. 263-267.
Ishikuro et al., “Fabrication of Nano-Scale Point Contact Metal-Oxide-Semiconductor Field-Effect-Transistors Using Micrometer-Scale Design Rule,” Japanese Journal of Applied Physics, vol. 38, Jan. 1999, pp. 396-398.
Kim et al., “Room Temperature Single Electron Effects in Si Quantum Dot Memory with Oxide-Nitride Tunneling Dielectrics,” IEEE, 1998, pp. 111-114.
Nakajima et al., “Si Single-Electron Tunneling Transistor with Nanoscale Floating Dot Stacked on a Coulomb Island y Self-Aligned Process,” American Vacuum Society, Sep./Oct. 1999, pp. 2163-2171.
Park et al., Enhancement of Coulomb Blockade and Tunability by Multidot Coupling in a Silicon-on-Insulator-Based Single-Electron Transistor, American Inst. of Physics, Applied Physics Letters, vol. 75, No. 4, 1999, pp. 566-568.
Pooley et al., “Coulomb Blockade in Silicon Nano-Pillars,” American Inst. of Physics, Applied Physics Letters, vol. 74, No. 15, Apr. 1999, pp. 2191-2193.
Prins et al., “Thermal Oxidation of Silicon-On-Insulator Dots,” Nanotechnology 10, 1999, pp. 132-134.
Takahashi et al., “Silicon Single-Electron Devices,” Int'l. Journal of Electronics, vol. 86, No. 5, 1999, pp. 605-639.
Welser et al., “Room Temperature Operation of a Quantum-Dot Flash Memory,” IEEE Electron Device Letters, vol. 18, No. 6, Jun. 1997, pp. 278-280.
Fraboulet David
Mariolle Denis
Morand Yves
Commissariat a l''Energie Atomique
Smoot Stephen W.
STMicroelectronics
Thelen Reid & Priest LLP
LandOfFree
Method for making an island of material confined between... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making an island of material confined between..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making an island of material confined between... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3593324