Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2000-10-13
2002-11-05
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Reexamination Certificate
active
06475827
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing packaged semiconductors and, more particularly but not by way of limitation, to an improved method of manufacturing packaged semiconductors which results in increase yield and expedited package defect testing
2. History of Related Art
It is conventional in the electronic industry to encapsulate one or more semiconductor devices, such as integrated circuit dies, or chips, in a semiconductor package. These plastic packages protect a chip from environmental hazards, and provide a method of and apparatus for electrically and mechanically attaching the chip to an intended device. Recently, such semiconductor packages have included metal lead frames for supporting an integrated circuit chip which is bonded to a chip paddle region formed centrally therein. Bond wires which electrically connect pads on the integrated circuit chip to individual leads of the lead frame are then incorporated. A hard plastic encapsulating material, or encapsulant, which covers the bond wire, the integrated circuit chip and other components, forms the exterior of the package. A primary focus in this design is to provide the chip with adequate protection from the external environment in a reliable and effective manner.
As set forth above, the semiconductor package therein described incorporates a lead frame as the central supporting structure of such a package. A portion of the lead frame completely surrounded by the plastic encapsulant is internal to the package.
Portions of the lead frame extend internally from the package and are then used to connect the package externally. More information relative to lead frame technology may be found in Chapter 8 of the book
Micro Electronics Packaging Handbook,
(1989), edited by R. Tummala and E. Rymaszewski, and incorporated by reference. This book is published by Van Nostrand Reinhold, 115 Fifth Avenue, New York, N.Y.
Once the integrated circuit chips have been produced and encapsulated in semiconductor packages described above, they may be used in a wide variety of electronic appliances. The variety of electronic devices utilizing semiconductor packages has grown dramatically in recent years. These devices include cellular phones, portable computers, etc. Each of these devices typically include a motherboard on which a significant number of such semiconductor packages are secured to provide multiple electronic functions. These electronic appliances are typically manufactured in reduced sizes and at reduced costs, consumer demand increases. Accordingly, not only are semiconductor chips highly integrated, but also semiconductor packages are highly miniaturized with an increased level of package mounting density.
According to such miniaturization tendencies, semiconductor packages, which transmit electrical signals from semiconductor chips to motherboards and support the semiconductor chips on the motherboards, have been designed to have a small size. By way of example only, such semiconductor packages may have a size on the order of 1×1 mm to 10×10 mm. Examples of such semiconductor packages are referred to as MLF (micro leadframe) type semiconductor packages and MLP (micro leadframe package) type semiconductor packages. Both MLF type semiconductor packages and MLP type semiconductor packages are generally manufactured in the same manner.
During the manufacturing for a semiconductor package, electrical testing is required to insure proper function of the semiconductor package. This testing occurs after the semiconductor package has been separated from a matrix of semiconductor packages by singulation. Because of this limitation, a multitude of semiconductor packages must be individually tested. The time required to individually test these packages, in addition to the small size of the packages, results in decreased efficiency and higher costs.
SUMMARY OF THE INVENTION
In one embodiment of the present invention, there is provided a method for manufacturing semiconductor packages. First, a plurality of unit leadframes in a matrix is provided.
A substantially planar die pad is within each unit leadframe and connected to the leadframe by a plurality of tie bars. A plurality of finger-like rectangular tabs extend from the unit leadframe towards the die pad without contacting the die pad. A semiconductor chip having a plurality of bond pads is mounted on a first surface of the die pad in the unit leadframe. Dam bars are provided on the boundary of the tabs to limit flow of encapsulation material during packaging.
Next, a bond wire or equivalent conductor is connected electrically between each bond pad of the semiconductor chip and a first surface of one of the tabs.
The unit leadframes are then encapsulated by a viscous encapsulant material. The encapsulant material is then hardened. The encapsulant material covers the semiconductor chip, the bond wires, a first surface of the tabs, the first surface of the die pad, the side surfaces of the die pad and tabs, and all or part of the frames around the die pad. A lower second surface of the unit leadframe, including a lower second surface of the die pad and tabs, may optionally be covered with the encapsulant material, but may not be covered depending on the requirements of the practitioner.
The unit packages are then singulated from the matrix. The singulation step first comprises the step of cutting the dam bars and the boundary areas between the tabs in the unit leadframe on two X-axes simultaneously, while leaving the connection between the tie bars and the unit leadframe intact. Next, the dam bars and boundary areas between the tabs in the unit leadframe are cut simultaneously on two Y-axes while leaving the connection between the tie bars and the unit leadframe intact. Electrical testing is next performed on the entire matrix. Finally, the tie bars are cut to individually separate independent semiconductor packages from the leadframe matrix.
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Lee Tae Heon
Seo Mu Hwan
Amkor Technology Inc.
Jenkens & Gilchrist P.C.
Niebling John F.
Stevenson Andre′ C
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