Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2005-12-13
2005-12-13
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S216000, C438S287000, C438S591000
Reexamination Certificate
active
06974764
ABSTRACT:
A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, and forming a first metal layer on a first part of the dielectric layer, leaving a second part of the dielectric layer exposed. After a second metal layer is formed on both the first metal layer and the second part of the dielectric layer, a masking layer is formed on the second metal layer.
REFERENCES:
patent: 5625217 (1997-04-01), Chau et al.
patent: 5753560 (1998-05-01), Hong et al.
patent: 5783478 (1998-07-01), Chau et al.
patent: 5891798 (1999-04-01), Doyle et al.
patent: 6048769 (2000-04-01), Chau
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6087261 (2000-07-01), Nishikawa et al.
patent: 6121094 (2000-09-01), Gardner et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6258643 (2001-07-01), Hsu
patent: 6306742 (2001-10-01), Doyle et al.
patent: 6383879 (2002-05-01), Kizilyalli et al.
patent: 6391802 (2002-05-01), Delpech et al.
patent: 6420279 (2002-07-01), Ono et al.
patent: 6436777 (2002-08-01), Ota
patent: 6475874 (2002-11-01), Xiang et al.
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6544906 (2003-04-01), Rotondaro et al.
patent: 6617209 (2003-09-01), Chau et al.
patent: 6617210 (2003-09-01), Chau et al.
patent: 6642131 (2003-11-01), Harada
patent: 6667246 (2003-12-01), Mitsuhashi et al.
patent: 6727130 (2004-04-01), Kim et al.
patent: 6780699 (2004-08-01), Tamura et al.
patent: 6794234 (2004-09-01), Polishchuk et al.
patent: 2002/0135023 (2002-09-01), Madhukar et al.
patent: 2002/0197790 (2002-12-01), Kizilyalli et al.
patent: 2003/0032303 (2003-02-01), Yu et al.
patent: 2003/0045080 (2003-03-01), Visokay et al.
patent: 2004/0106249 (2004-06-01), Huotari
Polishchuk et al. “Dual Workfunction CMOS Gate Technology Based on Metal Interdiffusion,” www.eesc.berkeley.edu, 1 page.
Doug Barlage et al., “High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics”, 2001 IEEE, 4 pages.
Robert Chau et al., A 50nm Depleted-Substrate CMOS Transistor (DST), 2001 IEEE, 4 pages.
Lu et al., “Dual-Metal Gate Technology for Deep-Submicron CMOS Devices”, dated Apr. 29, 2003, 1 page.
Schwantes et al., “Performance Improvement of Metal Gate CMOS Technologies with Gigabit Feature Sizes”, Technical University of Hanburg-Harburg, 5 pages.
Parker et al., “A Method of Making Semiconductor Device Having a High-K Gate Dielectric”, U.S. Appl. No. 10/285,915, filed Oct. 31, 2002.
Chau et al., “A Method of Making Semiconductor Device Having a High-K Gate Dielectric”, U.S. Appl. No. 10/288,043, filed Nov. 5, 2002.
Parker et al., “A Method of Making Semiconductor Device Having a High-K Gate Dielectric”, U.S. Appl. No. 10/315,268, filed Dec. 10, 2002.
Doczy et al., “A Method of Making Semiconductor Device Having a High-K Gate Dielectric”, U.S. Appl. No. 10/338,174, filed Jan. 7, 2003.
Brask et al., “A Method of Making Semiconductor Device Having a High-K Gate Dielectric”, U.S. Appl. No. 10/387,303, filed Mar. 11, 2003.
Brask et al., “A Method of Making Semiconductor Device Having a High-K Gate Dielectric”, U.S. Appl. No. 10/391,816, filed Mar. 18, 2003.
Chau et al., “A Method for Making a Semiconductor Device Having a Metal Gate Electrode”, U.S. Appl. No. 10/431,166, filed May 6, 2003.
Brask, et al, “A Method for Making a Semiconductor Device Having a High-K Gate Dielectric”, U.S. Appl. No. 10/441,616, filed May 20, 2003.
Brask et al. “A Selective Etch Process for Making a Semiconductor Device Having a High-K Gate Dielectric,” U.S. Appl. No. 10/652,546, filed Aug. 28, 2003.
Brask et al. “A Method for Making a Semiconductor Device Having a High-K Gate Dielectric,” U.S. Appl. No. 10/642,796, filed Aug. 28, 2003.
Brask, “Methods and Compositions for Selectively Etching Metal Films and Structures,” U.S. Appl. No. 10/658,225, filed Sep. 8, 2003.
Brask Justin K.
Chau Robert S.
Doczy Mark L.
Kavalieros Jack
Metz Matthew V.
Intel Corporation
Picardat Kevin M.
Plimier Michael D.
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