Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-03-27
2008-10-28
Kebede, Brook (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S411000, C257SE21010, C257SE21194
Reexamination Certificate
active
07442983
ABSTRACT:
A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.
REFERENCES:
patent: 6063698 (2000-05-01), Tseng et al.
patent: 6184072 (2001-02-01), Kaushik et al.
patent: 6255698 (2001-07-01), Gardner et al.
patent: 6340827 (2002-01-01), Choi et al.
patent: 6365450 (2002-04-01), Kim
patent: 6410376 (2002-06-01), Ng et al.
patent: 6420279 (2002-07-01), Ono et al.
patent: 6475874 (2002-11-01), Xiang et al.
patent: 6514828 (2003-02-01), Ahn et al.
patent: 6544906 (2003-04-01), Rotondaro et al.
patent: 6559014 (2003-05-01), Jeon
patent: 6586288 (2003-07-01), Kim et al.
patent: 6617209 (2003-09-01), Chau et al.
patent: 6617210 (2003-09-01), Chau et al.
patent: 6620713 (2003-09-01), Arghavani et al.
patent: 6689675 (2004-02-01), Parker et al.
patent: 6696327 (2004-02-01), Brask et al.
patent: 6696345 (2004-02-01), Chau et al.
patent: 6709911 (2004-03-01), Doczy et al.
patent: 6713358 (2004-03-01), Chau et al.
patent: 6716707 (2004-04-01), Brask et al.
patent: 6746967 (2004-06-01), Brask et al.
patent: 6770568 (2004-08-01), Brask
patent: 2002/0058374 (2002-05-01), Kim et al.
patent: 2002/0086504 (2002-07-01), Park et al.
patent: 2002/0197790 (2002-12-01), Kizilyalli et al.
patent: 2003/0032303 (2003-02-01), Yu et al.
patent: 2003/0045080 (2003-03-01), Visokay et al.
patent: 2004/0087124 (2004-05-01), Kubota
patent: 2005/0074978 (2005-04-01), Wang et al.
patent: 0 899 784 AZ (1999-03-01), None
patent: 2 358 737 (2001-04-01), None
Polishchuk et al., “Dual Workfunction CMOS Gate Technology Based on Metal Interdiffusion”, www.eesc.berkeley.edu, 1 page.
Doug Barlage et al., “High-Frequency Response of 100nm Integrated CMOS Transistors with High-K Gate Dielectrics”, 2001 IEEE, 4 pages.
Lu et al., “Dual-Metal Gate Technology for Deep-Submicron CMOS Devices”, dated Apr. 29, 2003, 1 page.
Schwantes et al., “Performance Improvement of Metal Gate CMOS Technologies with Gigabit Feature Sizes”, Technical University of Hanburg-Harburg, 5 pages.
Brask Justin K.
Chau Robert S.
Datta Suman
Dewey Gilbert
Doczy Mark L.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Kebede Brook
LandOfFree
Method for making a semiconductor device having a high-k... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for making a semiconductor device having a high-k..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for making a semiconductor device having a high-k... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3988765