Method for making a semiconductor device

Details Method for making a semiconductor device Method for making a semiconductor device

1998-01-20

2001-01-09

Saadat, Mahshid (Department: 2815)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S592000, C438S471000, C438S649000, C438S751000

Reexamination Certificate

active

06171959

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor manufacturing, and more particularly to, a depositing both cobalt and titanium layers when forming cobalt silicide MOS source and drain regions to prevent or reduce unwanted residue formation on an integrated circuit (IC).
BACKGROUND OF THE INVENTION
In the integrated circuit (IC) industry, it is advantageous to form silicided or salicided source regions, drain regions, and gate electrodes to reduce series resistance and contact resistance whereby integrated circuits with greater performance can be fabricated. Once such method for forming salicided source, drain, gate electrodes in an MOS transistor is illustrated in prior art FIGS.
1
-
3
.
FIG. 1
illustrates a prior art structure
10
which has a substrate
12
. Source and drain regions
14
and
16
are formed within the substrate
12
.
FIG. 1
illustrates field oxide isolation regions
17
and a gate oxide
18
formed over the substrate
12
. A gate electrode
20
is formed over the gate oxide
18
where the gate electrode
20
is laterally surrounded by an oxide region
22
and a dielectric spacer
24
. In order to enable formation of silicide regions over the regions
14
,
16
, and
20
, a cobalt metallic layer
26
a
is deposited as illustrated in FIG.
1
. The cobalt layer
26
a
is then capped with a titanium nitride (TiN) layer
28
.
The titanium nitride (TiN) layer
28
is used to cap the cobalt layer
26
a
for one of many reasons. First, cobalt is sensitive to oxygen ambients, and cobalt will adversely oxidize in O
2
ambients whereby the titanium nitride layer
28
prevents this adverse oxidation of layer
26
a
. The titanium nitride layer
28
also imparts advantageous stress on the underlying layer
26
a
to modulate the diffusion of the cobalt species in an improved manner as compared to structures that contain no capping layer
28
. Therefore, unwanted lateral diffusion of unreacted cobalt is reduced due to the presence of the capping layer
28
in the silicide process shown in FIGS.
1
-
3
.
FIG. 2
illustrates that a thermal environment
29
is used to react the cobalt in the layer
26
a
with the regions
14
,
16
, and
20
. This thermal process
29
reacts some of the cobalt in layer
26
a
to form cobalt silicide regions
30
,
32
, and
36
as illustrated in FIG.
2
and leaves behind some unreacted cobalt. Layer
26
b
of
FIG. 2
illustrates that some cobalt from the layer
26
a
in
FIG. 1
may remain unreacted with silicon and therefore remain overlying the structure
10
. It is important to note that there is no gettering or mixing between the titanium nitride layer
28
and the cobalt layer
26
a
or
26
b
in
FIG. 2
to prevent unreacted cobalt from being in contact with the oxide
17
or the spacer
24
during thermal processing
29
.
FIG. 3
illustrates that an etch process is then used to remove the titanium nitride layer
28
and the unreacted cobalt layer
26
b
from the device
10
. Since unreacted cobalt is exposed to surface portions of the silicon nitride spacer
24
and the field oxide region
17
during silicidation, some cobalt residue
38
is left on the spacer
24
and on field oxide portion
17
. This residue has proven impossible to remove from the device regardless of how long etch processing and/or wet cleaning procedures are performed. Therefore, although the TiN/Co process of FIGS.
1
-
3
has some advantages as discussed above, the residual remains
38
of the process of FIGS.
1
-
3
are disadvantageous for various reasons discussed below.
The process of FIGS.
1
-
3
is not an optimal silicide process since the process of FIGS.
1
-
3
will leave behind cobalt residue
38
on the sidewall spacer
24
and over the field oxide regions
17
(see FIG.
3
). A process is desired which can remove or reduce the presence of this conductive cobalt residue
38
which could otherwise cause electrical short between devices. In addition, the process of FIGS.
1
-
3
is also disadvantageous as the required thermal process
39
must be a low temperature one to obtain shallow silicided regions that have higher performance. Typically, the temperature used for the environment
29
can not exceed 500 degrees Celsius. Low temperature processing enables unreacted cobalt to diffuse into areas adjacent to layer
26
a
and cause cobalt/cobalt silicide spiking which could increase the diode leakage and/or degrade the device performance. Hence an high temperature process is required so that metal-silicon reaction dominates over the metal diffusion in silicon, while still obtaining a thin silicide.
Since the titanium nitride layer
28
and the cobalt layer
26
a
do not chemically interact or mix in
FIG. 2
, in addition to the undesirable lateral diffusion of cobalt, residual cobalt
38
is left behind on the oxide
17
and the spacer
24
as shown in FIG.
3
. Therefore, the lack of cobalt gettering on the nitride
24
and oxide
17
regions, as shown in the process of FIGS.
1
-
3
, leads to the residue formation of FIG.
3
. It is important, to note that the residue
38
in
FIG. 3
is most likely to be conductive in nature, and will increase capacitive coupling and leakage current between the gate electrode
20
and the source and drain regions
14
and
16
. In some cases, the residue
38
may form a complete electrical short circuit between the gate electrode
20
and the source and drain regions
14
and
16
. Therefore, avoidance or reduction of residue
38
is desired in a salicide process.
Furthermore, subsequent processing of the device of
FIG. 3
may supply silicon atoms and/or heat to the residue
38
whereby the contamination
38
may diffuse, grow, and/or spread along the sidewall of the spacer
24
whereby short circuits between the gate
20
and the source and drain regions
14
and
16
become more likely and/or more damaging to IC yield. Due to this effect, high temperature dopant drive cycles to move dopant atoms out of a cobalt silicide layers to form shallow source and drain regions
14
and
16
cannot be used with adequate yield in FIGS.
1
-
3
. This yield loss is due to the fact that the high temperatures used to diffuse dopant atoms would diffuse/spread the residue
38
and increase the leakage current and electrical shorts between regions
14
,
16
, and
20
.
In addition, due to the lack of gettering and the problems discussed above, the layer
26
a
of
FIG. 1
must be deposited very thin and as typically less than 100 angstroms in thickness. Any deposition of thin metallic materials is difficult to maintain within proper standard deviations given current deposition process chambers and technology. Therefore, a process which enables thicker deposition of cobalt layer, still obtaining a thin silicide, is more desirable.
In summary, the process of FIGS.
1
-
3
is disadvantageous for the reasons discussed above and a new process which reduces or avoids these disadvantages is desired in the integrated circuit (IC) industry.
As an additional point related to the process taught hereinbelow, there may be structures which contain both titanium and cobalt in a single metallic stack. However, the industry has not used a titanium-cobalt bilayer stack to perform cobalt-gettered selective salicidation where desirable complete gettering of cobalt over the spacer
24
and oxide reins
17
is accomplished along with the silicide formation process. Furthermore, gettered formation and complete subsequent removal of any titanium-cobalt/titanium-cobalt-silicon intermetallic composite material formed during the anneal is essential and a technique for enabling such removal has not been addressed by the prior art. In addition, the use of titanium-cobalt stacks to avoid the residue contamination problems discussed herein via gettering of cobalt adjacent nitride or oxide interfaces has not been identified or addressed in the prior art.


REFERENCES:
patent: 5047367 (1991-09-01), Wei et al.
patent: 5384285 (1995-01-01), Sitaram et al.
patent: 5567651 (1996-10-01), Berti et al.
patent: 5874342 (1999-02-01), Ts

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