Method for maintaining multi-level cache coherency in a processo

Details Method for maintaining multi-level cache coherency in a processo Method for maintaining multi-level cache coherency in a processo

1997-09-18

2000-05-16

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711118, 711119, 711123, 711141, 711146, G06F 1300

Patent

active

060650982

ABSTRACT:
The processor includes at least a lower and a higher level non-inclusive cache, and a system bus controller. The system bus controller snoops commands on the system bus, and supplies the snooped commands to each level of cache. Additionally, the system bus controller receives the response to the snooped command from each level of cache, and generates a combined response thereto. When generating responses to the snooped command, each lower level cache supplies its responses to the next higher level cache. Higher level caches generate their responses to the snooped command based in part upon the response of the lower level caches. Also, high level caches determine whether or not the cache address, to which the real address of the snooped command maps, matches the cache address of at least one previous high level cache query. If a match is found by a high level cache, then the high level cache generates a retry response to the snooped command, which indicates that the snooped command should be resent at a later point in time, in order to prevent a collision between cache queries.

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