Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-02-10
1999-04-13
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711141, 395308, G06F 1316, G06F 1340
Patent
active
058939210
ABSTRACT:
A method for maintaining memory coherency in a data processing system is disclosed. The data processing system includes a memory system having a dual bus memory controller, which is coupled to a first bus through a first bus master and a second bus coupled to a second bus master. The method maintains memory coherency by snooping across either the first or second bus for attributes on an address/data multiplex bus in the data processing unit. To determine when a snoop operation is required, the system begins by requesting access to either of the two buses through the dual bus memory controller. Once the control of the bus has been granted upon request data is transferred using the master bus controller. It is upon the receipt of an invalid data signal while transferring data across the bus that the snoop activity begins. The snoop is injected only after an invalid data signal is received and a last snoop injection can occur only before a last read data is read.
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Bucher Timothy
Hester Douglas Christopher
Sell John Victor
Tran Cang N.
Dillon Andrew J.
International Business Machines - Corporation
Peikari J.
Salys Casimer K.
Swann Tod R.
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