Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-05-15
2003-02-25
Thomas, Tom (Department: 2811)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06526546
ABSTRACT:
The present invention relates to a process for locating a defective element in an integrated circuit whose theoretical layout is known, of the type comprising a succession of steps consisting in:
the determination of a measurement point of the integrated circuit; and
the testing of the measurement point determined by implementing:
the application of a sequence of tests to the inputs of the integrated circuit;
the measurement of signals at the determined measurement point of the integrated circuit, during the application of the sequence of tests; and
the assessment of the measurement point by comparison of the measured signals with theoretical signals which ought to be obtained at the determined measurement point so as to assess whether the measurement point is faulty or satisfactory; and
in which the position of the defective element of the integrated circuit is determined from assessments performed at the various determined measurement points.
It is expedient, in the manufacture of integrated circuits, or when searching for faults in industrial systems, to be able to determine the origin of defects or breakdowns.
In particular, in the case of defective integrated circuits, it is necessary to be able to determine which component or components constituting the integrated circuit exhibit an operating anomaly.
The number of components involved in the construction of an integrated circuit is generally very high so that it is very tricky to locate the one or the few defective elements from among the multitude of elements from which the breakdown may result.
A process for analysing integrated circuits, known by the English term “backtracking”, is currently known. To implement this process, a testing rig is used, making it possible with the aid of hardware or virtual probes to plot signals flowing at various circuit measurement points.
By knowing the theoretical structure of the integrated circuit analysed, the signals which ought to be measured at the various circuit measurement points are determined as a function of a sequence of tests applied to the inputs of the circuit.
In order to locate the defective elements in the circuit, a defective output of the circuit is first considered and then we backtrack from this output to the inputs, gradually testing each of the successive measurement points. As long as the measurements performed at the various points reveal signals which are incorrect as compared with the theoretical signals which ought to be obtained, one deduces that the defective elements of the circuit are upstream of the measurement point. As soon as correct signals are obtained at a measurement point, one deduces that the defective element is situated between the measurement point where correct signals are obtained and the previous measurement point where incorrect measurement signals were obtained.
Each measurement actually performed on the integrated circuit requires a considerable time which may range from a few seconds if the measurement point is at the surface to 5 to 10 minutes if the measurement point is situated on a deep layer of the integrated circuit and if a prior hardware port must be made with the aid, for example, of a focused ion beam.
It is appreciated that, with the method currently used, it is sometimes necessary to traverse back through the nub of the integrated circuit if the defective element is very close to an input of the circuit. Owing to the complexity of the circuits and their numerous constituent branches, the search for the defective element may prove to be extremely lengthy.
The aim of the invention is to propose a process for detecting errors in a circuit allowing faster locating of defective zones, whilst preserving great reliability in this locating.
Accordingly, the subject of the invention is a process of the aforesaid type, characterized in that it comprises initially:
a step of modelling the theoretical layout of the integrated circuit, in the form of at least one graph comprising a set of nodes and of arcs oriented from the inputs of the circuit to the outputs of the circuit;
considering as a search subgraph, a subgraph whose vertex-forming node corresponds to a faulty measurement point;
and in that, for the search for the defective element, it comprises the steps of:
assigning each node of the search subgraph considered a characteristic variable dependent on the structure of the search subgraph;
considering as measurement point the measurement point corresponding to a node of the subgraph considered, obtained by applying a predetermined criterion pertaining to the characteristic variables of the set of nodes of the search subgraph considered;
performing a test of the measurement point considered;
considering as new search subgraph:
either the search subgraph previously considered, while excluding the node corresponding to the measurement point tested and all its parent nodes, if the measurement point is satisfactory
or a subgraph whose node corresponding to the measurement point is the vertex, if the measurement point is faulty; and
searching for the defective element in the new search subgraph considered, until a predetermined stopping criterion is satisfied.
According to particular modes of implementation, the process comprises one or more of the following characteristics:
during the initial step of modelling the theoretical layout of the integrated circuit, the circuit is modelled the form of a tree by possible creation of virtual nodes when one and the same node is the parent of at least two nodes, themselves parents of one and the same node;
it comprises, after satisfaction of the predetermined stopping criterion, the steps of:
evaluating in the or each last search subgraph whether, for each virtual node corresponding to a faulty measurement point, the twin node associated with the said virtual node is a node of the same subgraph also corresponding to a faulty measurement point; and
then considering the or each subgroup for which the condition is satisfied as corresponding to a part of the integrated circuit comprising at least one defective element;
the said characteristic variable peculiar to each node is the number of ancestors of this node in the search subgraph considered;
the said predetermined criterion is suitable for determining the node whose number of ancestors is substantially equal to the mean number of ancestors per node in the search subtree considered;
it comprises a step of assigning each node a compliance indicator initially fixed at a faulty state; and
for the determination of the new search subgraph to be considered, it comprises the steps of:
fixing the compliance indicator of the node corresponding to the measurement point tested and of all its parent nodes at a satisfactory state, if the measurement point tested is satisfactory; and
considering as new search subgraph the subgraph included within the previous search subgraph and comprising only those nodes whose compliance indicator is fixed at the faulty state; and
the search subgraph initially considered is formed at the intersection of the subgraphs each having as vertex a node corresponding to a faulty output of the integrated circuit.
The subject of the invention is also a device for locating a defective element in an integrated circuit whose theoretical layout is known, of the type comprising means for performing a succession of steps consisting in:
the determination of a measurement point of the integrated circuit; and
the testing of the measurement point determined by implementing:
the application of a sequence of tests to the inputs of the integrated circuit;
the measurement of signals at the determined measurement point of the integrated circuit, during the application of the sequence of tests; and
the assessment of the measurement point by comparison of the measured signals with theoretical signals which ought to be obtained at the determined measurement point so as to assess whether the measurement point is faulty or satisfactory; and
means for determining the position of the defective element of the integrated circuit from assessments perform
Desplats Romain
Rolland Guy
Centre National d'Etudes Spatiales
Owens Douglas W.
Thomas Tom
Young & Thompson
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