Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-05-31
2002-01-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S666000, C438S668000, C438S669000, C257S734000, C257S773000, C257S774000, C257S775000
Reexamination Certificate
active
06340631
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method for laying out an IC circuit on a mask for use in a photolithographic process and more particularly, relates to a method for laying out metal lines that are wider than 5 &mgr;m with embedded contacts/vias on a photomask that has improved process window when used in a subsequent photolithographic process.
BACKGROUND OF THE INVENTION
In the continuing miniaturization of integrated circuit devices, the circuit layout process becomes more stringent as the dimensions become smaller. The old requirements in design rules are being tightened, while new requirements are being initiated for the ever shrinking devices. A complete IC fabrication process usually requires between 10 to 20 masking steps according to the complexity of the device and the fabrication process. Each masking step introduces some changes in the surface dimensions, whether they are in the silica substrate or in the film layers deposited on top of the substrate. Minimal-dimension rules, as part of the design rules, are governed by the processing requirements or the physical property requirements of the IC device. For instance, when the minimal spacings are violated, in the case of wide metal lines on top of a silicon wafer, various problems can occur in the circuit operation. The wide metal lines generally refer to metal lines that have a width of at least 5 &mgr;m, or preferably at least 10 &mgr;m. In order to fabricate circuits that have high reliability, circuit designers use the minimal design rules for the construction of various layers on top of a silicon substrate.
While many design factors are involved in determining the minimal design rules, some of the most important factors includes the line-width tolerances, junction depth and lateral diffusion, thickness tolerances, and masking tolerances. For instance, the line-width dimension on a finished wafer usually differs from the corresponding line-width dimension on the photomask. This is due to the fact that the photolithographic and etching steps used to pattern the line generally shrink or expand the original line by a biased amount. Due to the statistical nature of the bias, the shrinkage or expansion produces another uncertainty of the line width. The amount of bias and uncertainty of the line width depend very much on the processing equipment and procedure.
The process window for a specific fabrication process is a very important parameter in achieving process reliability and control. When a specific processing equipment is used for performing a process, the performance of the equipment depends on many parameters. A small change in any of the process parameters may induce a corresponding change in the performance of the equipment. The window of operation for the specific equipment is therefore defined as the specific limits of the response induced by the change in parameter. For instance, when the photoresist of a masking layer is exposed in a stepper, the exposure dosage greatly affects the line width of the photoresist. Higher dosage produces smaller line width. In the operation of the stepper machine, there is therefore a specific range of dosage that can be used to obtain the acceptable line width. A term of sensitivity of the process therefore defines the incremental change of line width that occurs upon a change of dosage. In designing a manufacturing process, it is desirable to have as large a process window and as small a sensitivity as possible, in order to tolerate large variations in equipment performance.
One example of the desirability of a large process window is the photolithographic process for laying out wide metal lines on a semiconductor wafer. The wide metal lines, i.e., generally wider than 5 &mgr;m or preferably wider than 10 &mgr;m, cause a smaller photo process window than that normally found on narrower metal lines, i.e., in dimensions of less than 1 &mgr;m. The narrow process window for the wide metal lines can cause severe processing problems, such as forming metal lines that are easily bridged or having leakage between the lines. In order to avoid such problems, larger space rule has been used for laying out the wide metal lines. The problem is more severe when the wide metal lines are embedded with contacts or vias.
It is therefore an object of the present invention to provide a method for laying out wide metal lines that are imbedded with contacts/vias that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for laying out wide metal lines that are imbedded with contacts/vias on a photomask that has improved process window.
It is a further object of the present invention to provide a method for laying out wide metal lines that are imbedded with contacts/vias on a photomask by utilizing zig-zag bordered metal lines.
It is another further object of the present invention to provide a method for laying out wide metal lines that are imbedded with contacts/vias on a photomask that has improved process window by utilizing a zig-zag bordered metal line that forms waveformed borders after exposure on a wafer surface.
It is still another object of the present invention to provide a method for laying out wide metal lines that are imbedded with contacts/vias on a photomask with improved process window by providing zig-zag bordered metal lines such that each contact/via is positioned juxtaposed to a corresponding contacts/vias in an adjacent metal line.
It is yet another object of the present invention to provide a method for laying out wide metal lines that are imbedded with contacts/vias on a photomask with improved process window by using zig-zag bordered metal lines such that a contact/via in the first metal line is positioned juxtaposed to a spacing between contacts/vias in an adjacent second metal line.
It is still another further object of the present invention to provide a semiconductor wafer that has patterns of wide metal lines exposed thereon which include a first metal line exposed on the wafer surface that has a first plurality of contacts/vias embedded therein wherein each of the contacts/vias is positioned juxtaposed to a corresponding contact/via in an adjacent second metal line.
It is yet another further object of the present invention to provide a semiconductor wafer that has patterns of wide metal lines exposed thereon which includes a first metal line exposed on the wafer surface that has a first plurality of contacts/vias embedded therein such that each of the contacts/vias is positioned juxtaposed to a spacing between contacts/vias in an adjacent second metal line.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for laying out wide metal lines embedded with contacts/vias on a photomask with improved process window and semiconductor substrates that have patterns of wide metal lines exposed thereon are provided.
In a preferred embodiment, a method for laying out wide metal lines imbedded with contacts/vias on a photomask with improved process window can be carried out by the operating steps of first laying out a first metal line that has zig-zag borders, a width of at least 5 &mgr;m and a first plurality of contacts/vias along at least one of two opposite edges of the line with the contacts/vias in protruded portions of the zig-zag on a photomask, each of the first plurality of contacts/vias is spaced from its immediate adjacent contact/via at a pre-set spacing, and laying out a second metal line that has zig-zag borders, a width of at least 5 &mgr;m and a second plurality of contacts/vias along at least one of two opposite edges of the line with the contacts/vias in protruded portions of the zig-zag on the photomask, each of the second plurality of contacts/vias is spaced from its immediate adjacent contact/via at the preset spacing, each of the second plurality of contacts/vias is further positioned to align either with a corresponding contact/via in the first metal line or a spacing between two adjacent contacts/vias in the firs
Chih-Po Huang
Hann-Huei Tsai
Tsung-Mu Lai
Gurley Lynne
Niebling John F.
Taiwan Semiconductor Manufacturing Company Ltd
Tung & Associates
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