Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2008-04-16
2010-06-29
Treat, William M (Department: 2181)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
Reexamination Certificate
active
07747840
ABSTRACT:
Methods for latest producer tracking in a processor. In one embodiment, the method includes the steps of (1) writing a physical register identification value in a first register rename map location specified by a first instruction, (2) writing a first in-register status value in a second register rename map location specified by the first instruction, (3) writing a producer tracking status value at a producer tracking map location specified by the physical register identification value, and (4) modifying, upon graduation of the first instruction, the first in-register status value only if the producer tracking map location stores the producer tracking status value written in step (3). Other methods are also presented.
REFERENCES:
patent: 5091851 (1992-02-01), Shelton et al.
patent: 5109520 (1992-04-01), Knierim
patent: 5325511 (1994-06-01), Collins et al.
patent: 5452426 (1995-09-01), Papworth et al.
patent: 5493523 (1996-02-01), Huffman
patent: 5493667 (1996-02-01), Huck et al.
patent: 5510934 (1996-04-01), Brennan et al.
patent: 5526504 (1996-06-01), Hsu et al.
patent: 5537538 (1996-07-01), Bratt et al.
patent: 5546545 (1996-08-01), Rich
patent: 5568630 (1996-10-01), Killian et al.
patent: 5572704 (1996-11-01), Bratt et al.
patent: 5586278 (1996-12-01), Papworth et al.
patent: 5604909 (1997-02-01), Joshi et al.
patent: 5606683 (1997-02-01), Riordan
patent: 5632025 (1997-05-01), Bratt et al.
patent: 5670898 (1997-09-01), Fang
patent: 5675759 (1997-10-01), Shebanow et al.
patent: 5734881 (1998-03-01), White et al.
patent: 5740402 (1998-04-01), Bratt et al.
patent: 5758112 (1998-05-01), Yeager et al.
patent: 5764999 (1998-06-01), Wilcox et al.
patent: 5765037 (1998-06-01), Morrison et al.
patent: 5781753 (1998-07-01), McFarland et al.
patent: 5784584 (1998-07-01), Moore et al.
patent: 5799165 (1998-08-01), Favor et al.
patent: 5802339 (1998-09-01), Sowadsky et al.
patent: 5802386 (1998-09-01), Kahle et al.
patent: 5809326 (1998-09-01), Nogami
patent: 5809336 (1998-09-01), Moore et al.
patent: 5881257 (1999-03-01), Glass et al.
patent: 5884061 (1999-03-01), Hesson et al.
patent: 5954815 (1999-09-01), Joshi et al.
patent: 5961629 (1999-10-01), Nguyen et al.
patent: 5966734 (1999-10-01), Mohamed et al.
patent: 5974535 (1999-10-01), Peng et al.
patent: 6044478 (2000-03-01), Green
patent: 6076159 (2000-06-01), Fleck et al.
patent: 6079014 (2000-06-01), Papworth et al.
patent: 6085315 (2000-07-01), Fleck et al.
patent: 6216200 (2001-04-01), Yeager
patent: 6223278 (2001-04-01), Morrison
patent: 6247124 (2001-06-01), Joshi et al.
patent: 6249862 (2001-06-01), Chinnakonda et al.
patent: 6266755 (2001-07-01), Yeager
patent: 6298438 (2001-10-01), Thayer et al.
patent: 6308252 (2001-10-01), Agarwal et al.
patent: 6393550 (2002-05-01), Fetterman
patent: 6430655 (2002-08-01), Courtright et al.
patent: 6473837 (2002-10-01), Hughes et al.
patent: 6477639 (2002-11-01), Krishnan et al.
patent: 6505285 (2003-01-01), Rabinovici et al.
patent: 6546477 (2003-04-01), Russo et al.
patent: 6557127 (2003-04-01), Adams et al.
patent: 6594728 (2003-07-01), Yeager
patent: 6598148 (2003-07-01), Moore et al.
patent: 6691221 (2004-02-01), Joshi et al.
patent: 6757817 (2004-06-01), Booth
patent: 6760835 (2004-07-01), Yu
patent: 6836833 (2004-12-01), Kinter et al.
patent: 6915395 (2005-07-01), Singh
patent: 7032226 (2006-04-01), Nemirovsky et al.
patent: 7370178 (2008-05-01), Svendsen et al.
patent: 7401205 (2008-07-01), Dally et al.
patent: 7502876 (2009-03-01), Nemirovsky et al.
patent: 2003/0149862 (2003-08-01), Kadambi
patent: 2004/0128483 (2004-07-01), Grochowski et al.
patent: 2004/0193858 (2004-09-01), Ahmad et al.
patent: 2005/0102483 (2005-05-01), Kinter et al.
patent: 2006/0095732 (2006-05-01), Tran et al.
patent: 2006/0149904 (2006-07-01), Mowry
patent: 2006/0259747 (2006-11-01), Gonzalez et al.
patent: 2008/0016326 (2008-01-01), Svendsen et al.
patent: 2322718 (1998-09-01), None
patent: 02/082278 (2002-10-01), None
Shen et al., Modern Processor Design, McGraw-Hill, published Jul. 7, 2009, pp. 239-242 and 254-259.
ADSP-21535 Blackfin™DSP Brochure, Analog Devices, Inc., 4 pages (2001).
Andes R10000 User's Manual, Revision 2.0, MIPS Technologies, Inc., Entire Text (Sep. 19, 1996).
Arvind, A. and Maessen, J.-W., “Memory Model = Instruction Reordering + Store Atomicity,”ACM SIGARCH Computer Architecture News, vol. 34, Issue 2, pp. 29-40 (May 2006).
Banakar, R. et al., “Scratchpad Memory: A Design Alternative for Cache On-chip memory in Embedded Systems,”Proceedings of CODES'02, ACM, Estes Park, Colorado, pp. 73-78 (May 2002).
Bellas, N. et al., “Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors,”IEEE Trans. on Very Large Scale Integration(VLSI) Systems, vol. 8, No. 3, pp. 317-326 (Jun. 2000).
Bird, P.L. et al., “The Effectiveness of Decoupling,”Proceedings of the 7th Int'l Conference on Supercomputing, pp. 47-56, ACM Press, New York, NY (1993).
Bratt, J.P. et al., U.S. Appl. No. 08/168,094, filed Dec. 15, 1993, entitled “Superscalar Microprocessor Instruction Pipeline Including Instruction Dispatching and Kill Control”.
Buti, T.N. et al., “Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors,”IBM J. Res. & Dev. 49(1):167-188, International Business Machines Corporation (Jan. 2005).
Cotterell, S. and Vahid, F., “Tuning of Loop Cache Architecture to Programs in Embedded System Design,”ISSS'02, 6 pp. (Oct. 2002).
Courtright, D., “Introducing: the MIPS32™ 4Kc™ and MIPS32™ 4Kp™ Processor Cores 'Jade',” paper copy of slide presentation distributed at theEmbedded Microprocessor Forum, pp. 1-25 (May 1999).
De Vries, H.,Understanding the detailed Architecture of AMD's 64 bit Core, 85 pages, printed Oct. 16, 2007 from http://chip-architect.coM
ews/2003—09—21—Detailed—Architecture—of—AMDs—64bit—Core.html. (Sep. 21, 2003).
Flynn et al., “Using Simple Tools to Evaluate Complex Architectural Trade-Offs,” IEEE Micro, pp. 67-75 (Jul. - Aug. 2000).
Fukuoka, K. et al., “Leakage Power Reduction for Clock Gating Scheme on PD-SOLl”IEEE Computer Society Int'l Symp. on Circuits and Systems, pp. 613-616 (2004).
Goodman, J.R. et al., “Pipe: A VLSI Decoupled Architecture,”ACM SIGARCH Computer Architecture News, pp. 20-27, ACM Press, New York, NY (Jun. 1985).
Gwennap, L., “MIPS R10000 Uses Decoupled Architecture,”Microprocessor Report, vol. 8, No. 14, pp. 1-5 (Oct. 24, 1994).
Gwennap, L., “MIPS R12000 to Hit 300 MHz,”Microprocessor Report, vol. 11, No. 13, pp. 1-4 (Oct. 6, 1997).
Gwennap, L., “MIPS Roadmap Focuses on Bandwidth,”Microprocessor Report, pp. 1-3 (May 12, 1997).
Gwennap, L., “SGI Provides Overview of TFP CPU,”Microprocessor Report, vol. 7, No. 2, pp. 1-2 (Feb. 15, 1993).
Gwennap, L., “TFP Designed for Tremendous Floating Point,”Microprocessor Report, vol. 7, No. 11, pp. 1-5 (Aug. 23, 1993).
Intel Architecture Software Developer's Manual - vol. 2: Instruction Set Reference, Intel. Corporation, pp. 3-278 and 3-279 (1997).
Intel Architecture Software Developer's Manual, vol. 1-3, pp. 2-7, 2-10, 2-11, 2-12, 3- 320, 9-16, A-10, and A-20 (1999).
Intel® StrongARM® SA-1100 Microprocessor Developer's Manual, Intel Corporation, pp. i-xix, 1-1 through 1-7, 2-1 through 2-8, and 6-1 through 6-7 (Aug. 1999).
Kandemir, M. et al., “Dynamic Management of Scratch-Pad Memory Space,”Proceedings of the 38th Design Automation Conference, ACM, Las Vegas, Nevada, pp. 690-695 (Jun. 2001).
Kandemir, M. et al., “Exploiting Scratch Pad Memory Using Presburger Formulas,”Proceedings of ISSS'01, ACM, Montreal, Quebec, Canada, pp. 7-12 (Oct. 2001).
Kandemir, M. et al., “Exploiting Shared Scratch Pad Memory Space in Embedded Multiprocessor Systems,”Proceedings of the 39th Design Automati
Jiang Xing Yu
Svendsen Kjeld
MIPS Technologies Inc.
Sterne Kessler Goldstein Fox PLLC.
Treat William M
LandOfFree
Method for latest producer tracking in an out-of-order... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for latest producer tracking in an out-of-order..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for latest producer tracking in an out-of-order... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4248279