Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-12-28
2004-03-16
Norton, Nadine G. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S692000, C438S710000, C438S712000, C438S720000
Reexamination Certificate
active
06706639
ABSTRACT:
BACKGROUND OF THE INVENTION
Integrated circuits commonly use multilevel interconnections as a means for electrically interconnecting semiconductor devices which include active or passive circuit elements. High-density integrated circuits such as Dynamnic Random Access Memories (DRAMs) or Static Random Access Memories (SRAMs) are typically comprised of hundreds of thousands or millions of semiconductor devices on a silicon substrate. These high density integrated circuits can be manufactured using a Complementary Metal-Oxide Semiconductor (CMOS) process and typically involve the use of multiple layers of vertically stacked metal interconnects. Fabrication of CMOS integrated circuits typically involves many manufacturing steps which include repeated deposition or growth, patterning, and etching of thin films of semiconductor, polysilicon, metal, and dielectric materials to form the electrical circuitry which typically consists of n-channel and p-channel transistors and active and passive circuit elements. Typically, the steps to form the n-channel and p-channel transistors are completed before the interconnect metal is formed. While active and passive circuit elements may be fabricated at any time during the processing sequence depending on the particular type of element, active circuit elements such as magnetoresistive memory storage bits are typically fabricated at the third metal level after the n-charnel and p-channel transistors are formed.
Forming metal interconnect typically requires the repeated steps of deposition or growth, patterning and etching of metal, via and dielectric layers as necessary to connect the integrated circuit elements. Typically, after the n-channel and p-channel transistors have been patterned and etched, a dielectric layer (e.g., silicon oxide) is formed over the surface of the topography to provide dielectric isolation between the devices and the overlying interconnect conducting regions. Next, a contact layer is patterned into the dielectric layer to define openings in the dielectric layer where ohmic contacts will interconnect a first level of metal to the source, drain and gate regions of the n-channel and p-channel transistors. The contact layer patterning is accomplished by first depositing a photoresist layer over the dielectric layer. The photoresist is next selectively exposed to light through a patterned reticle having the desired layer pattern. After exposure, the photoresist is developed to form a resist mask for the desired layer pattern. The exposed layer is then etched to define the contact openings. The last step is to deposit and etch the contact metal.
Following the above process, the first level of metal is deposited, patterned and etched over the contact and dielectric layers. The first level of metal is positioned over the contacts to provide electrical interconnection between the first level of metal and the n-channel and p-channel devices. A second dielectric layer is next formed over the patterned first metal layer. After via holes are formed in the second dielectric layer to provide openings to the first metal layer, a conductive material, such as tungsten, is deposited to fill the via holes and form “tungsten plugs.” After the tungsten plugs are formed, a second metal layer is deposited, patterned and etched over the tungsten plugs and the first dielectric layer. The second layer of metal is positioned over and in physical contact with the tungsten plugs to provide electrical interconnection between the second layer of metal and the first layer of metal. The steps of deposition or growth, patterning, and etching of metal, via and dielectric layers is repeated as desired to provide the necessary interconnect to form the integrated circuit.
Magnetoresistive memory storage bits are typically fabricated at the third metal level stage because the ferromagnetic materials used to form the magnetoresistive memory storage bits require processing below 300 degrees C. The bits are developed through repeated deposition of multiple thin films which may include cobalt, copper, nickel, iron, or tantalum. Once the magnetoresistive bits are formed, the bits are typically interconnected as a series of “bit strings”, where each bit string may consist of 4, 8, or 16 bits. Each bit string is then interconnected through metal interconnect layers to the electrical circuits.
As successive metal interconnect layers are fabricated to interconnect magnetoresistive bits, smooth planar surfaces become increasingly difficult to maintain. The resulting uneven topographies create a variety of problems, all of which reduce integrated circuit functional yields and reliability. One problem that results is that photoresist material cannot be applied in a uniform fashion over uneven topographies. Thus, when the stops of patterning the photoresist to form a resist mask and etching the exposed layer occur, features of the exposed layer may not be completely etched due to the incomplete development of the photoresist.
Another problem that results is poor step coverage. Step coverage is defined as a measure of how well a metal or dielectric film conforms over a previous step and is represented by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over relatively flat horizontal regions. If the step coverage is too small in metal films, high current densities can result which can cause electromigration or high current-induced stress failure. Small step coverages also increase metal interconnect layer resistance which can decrease integrated circuit performance or result in total failure.
Still another problem that can occur after etching the dielectric layer to form the via holes is polymer residue damage to the via holes. After the via holes are etched, polymer residues which occur during the etching process can remain in the via hole resulting in poor contact resistance between the via fill metal and metal interconnect layer.
Yet another problem that can occur is oxidation of the via fill or metal interconnect layer material surfaces. After the via holes are etched and the tungsten fill metal is conformally deposited over the surface of the via-level dielectric layer, the tungsten is etched back or chemical mechanically polished back to the surface of the dielectric layer thus exposing the surface of the vias to oxidation.
Still yet another problem that can occur from the steps of patterning dielectric, via and metal layers is damage to underlying metal layers and film layers such as magnetoresistive thin film storage layers. To prevent this damage, an additional electrically conductive layer called a stop layer that is both chemically inert and physically hard must be formed to overlie the metal or film layers.
It is therefore an object of the present invention to provide a method for forming metal to metal interconnects which have high-current carrying capability and which are electromigration resistant.
It is another object of the present invention to provide a method for forming interlevel metal to metal interconnects which reduce the number of processing steps required by eliminating one or more levels of via photolithography and etch processing steps.
It is yet another object of the present invention to provide a method for forming interlevel metal to metal interconnects that provide smooth planar topographies and improved step coverage resulting in improved reliability and yield.
It is still yet another object of the present invention to provide a stop layer which prevents damage to underlying metal interconnect layers or magnetoresistive thin film storage layers by being both chemically inert and physically hard resulting in improved reliability and yield.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages of the prior art by providing a method for manufacturing a high current, electromigration resistant interconnect for a magnetoresistive memory. Additional features and advantages of the invention will be set forth in the description that follows, and will be apparent f
Mikelson Hans Peter
Parker Randall Scott
Wagner John Jeffery
Kamrath Alan
Norton Nadine G.
Rider Bennett LLP
Union Semiconductor Technology Corp.
Vinh Lan
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