Method for interconnecting conducting layers of an integrated ci

Adhesive bonding and miscellaneous chemical manufacture – Delaminating processes adapted for specified product – Delaminating in preparation for post processing recycling step

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29578, 29591, 156644, 156646, 156653, 156657, 1566591, 156668, 204192E, 357 71, 427 90, B44C 122, C03C 1500, C03C 2506, B29C 1708

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046054707

ABSTRACT:
An improved method for forming a conductive path through at least one layer of insulating material in an integrated circuit structure comprising a narrow portion and a sloped oversized portion of the conductive path. The method comprises forming the sloped oversize portion of the conductive path by defining an opening in a layer of photoresist material applied over the layer of insulating material, sloping the edges of the photoresist layer adjacent the opening to define an angle with the plane of the underlying insulating layer, and etching the photoresist layer and the insulating layer with an etchant capable of removing both materials to form the sloped oversized portion of the conductive path. The narrow portion of the conductive path is formed by etching at least a portion of the insulating layer to expose a selected section of the integrated circuit structure below the insulating layer. Either the oversized sloped portion or the narrow portion may be formed first. Planarization can be carried out prior to formation of the conductive path and/or during formation of the oversized sloped portion.

REFERENCES:
patent: 4451326 (1984-05-01), Gwozdz
patent: 4470874 (1984-09-01), Bartush et al.
patent: 4481070 (1984-11-01), Thomas et al.
patent: 4523975 (1985-06-01), Groves et al.

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