Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1999-03-25
2001-08-14
Dharia, Rupal (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S104000, C710S120000, C370S445000, C370S462000, C324S309000, C324S312000
Reexamination Certificate
active
06275884
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a method for data processing in general, and in particular to a method for interconnecting components within a data processing system. Still more particularly, the present invention relates to a method for interconnecting chips within a device and logical subcircuits within a chip.
2. Description of the Prior Art
Within a data processing system, various components, such as a processor, a system memory, etc., are typically interconnected with each other via a group of wires known as a bus. In fact, the technique of using a multi-drop bus to transmit data has been in common use since the early days of electronic computers. Two types of multi-drop buses are typically utilized in a data processing system, namely, a data bus and an address bus. As their names imply, the data bus is utilized to transmit data, and the address bus is utilized to transmit addresses. There are many advantages in using a single interconnecting scheme such as a multi-drop bus for interconnecting components within a data processing system. For example, new components can easily be added or even be ported between data processing systems that use a common multi-drop bus.
When interconnecting subcircuits within a chip, however, a multi-drop bussing scheme requires additional wiring to combine each individual source into the multi-drop bus for each destination. As a result, the wiring becomes more difficult with the increase in the width of the bus and the number of subcircuits. Without resorting to the prior art multi-drop bussing scheme, the present invention discloses an improved method for interconnecting components within a data processing system, chips within a device, and logical subcircuits within a chip.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a number of components is connected to an uni-directional bus. The uni-directional bus is arranged in a loop configuration. Each component has at least one node identification. Communications among these components are provided in the form of messages via a respective node identification. Each message includes a node identification field and a content field.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4538263 (1985-08-01), Gabrielli et al.
patent: 4885538 (1989-12-01), Hoenniger, III et al.
patent: 4933845 (1990-06-01), Hayes
patent: 5530887 (1996-06-01), Harper et al.
patent: 0716361A2 (1996-06-01), None
Craft David John
Voigt Wendel Glenn
Bracewell & Patterson L.L.P.
Dharia Rupal
International Business Machines - Corporation
Salys Casimer K.
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