Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-07-18
2004-07-06
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S759000, C257S760000
Reexamination Certificate
active
06759750
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of a semiconductor device and more particularly to a method for forming a low-K dielectric layers with improved thermal stability and structural strength by forming pillars, comprising material with good thermal stability and structural strength within the low-K dielectric layer.
2) Description of the Prior Art
Integrated circuits continue to increase in complexity each year. As applications develop for memories, microprocessors, and minicomputers there is an increasing demand for greater microminiaturization. The shrinking design rule for ULSI circuits has led to increased interconnection delay caused by parasitic capacitance of interconnection wiring. One way to reduce the interconnection delay is to reduce the dielectric constant of the dielectric layer between the device layer and the interconnect layer, or the interlayer dielectric (ILD). A great deal of work has been aimed at developing organic polymers for use as interlayer dielectrics because their dielectric constants (K) are generally lower than those of inorganic materials. However, poor chemical stability, thermal stability and structural (mechanical) strength have hindered the widespread use of organic polymers as interlayer dielectrics in microelectronic fabrication.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,602,423 (Jain) shows damascene conductors with embedded pillars to prevent erosion during chemical-mechanical polishing.
U.S. Pat. No. 5,827,776 (Bandyopadhyay et al.) shows a multilevel interconnect structure using staggered interconnects to reduce electric field coupling between interconnect lines.
U.S. Pat. No. 5,110,712 (Kessler et al.) shows a metal interconnect in a polymer, low-K dielectric layer.
U.S. Pat. No. 5,744,394 (Iguchi et al.) shows a dual damascene process for forming interconnections.
However, none of these patents disclose or suggest combining a polymer, low-K dielectric layer with pillars comprising material with superior thermal stability and structural strength to overcome the processing limitations associated with using polymer, low-K dielectric layers.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming an organic, low-K dielectric layer having improved thermal stability.
It is another object of the present invention to provide a method for forming an organic, low-K dielectric layer having improved structural strength.
It is another object of the present invention to provide a method for forming an organic, low-K dielectric layer having improved bondability of spin coating back-end materials.
It is another object of the present invention to provide a method for forming an organic low-K dielectric layer with improved thermal stability, structural strength, and spin coating back-end material bondability by embedding pillars in the organic, low-K dielectric layer comprising a material with good thermal stability, structural strength, and bondability.
It is yet another object of the present invention to provide a producible and economical method for forming an organic, low-K dielectric layer in a semiconductor fabrication process.
To accomplish the above objectives, the present invention provides a method for integrating low-K materials in semiconductor fabrication. The process begins by providing a semiconductor structure having a dielectric layer thereover, wherein the dielectric layer comprising an organic low-K material. The dielectric layer is patterned to form pillar openings. A pillar layer is deposited over the semiconductor structure; thereby filling the pillar openings with the pillar layer. The pillar layer is planarized to form pillars embedded in said dielectric layer. The pillar layer comprises a material having good thermal stability, good structural strength, and good bondability of spin coating back-end materials, improving the manufacturability of organic, low-K dielectrics in semiconductor fabrication. In one embodiment, the pillars are formed prior to forming dual damascene interlayer contacts. In another embodiment, pillars are formed simultaneously with interlayer contacts.
The present invention provides considerable improvement over the prior art. Embedded pillars provide the thermal stability and structural strength necessary to make the use of organic, low-K dielectric layers practical, without reducing the dielectric properties of the organic, low-K dielectric layer. Also, the embedded pillars can provide good bondability of spin coating back-end materials.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5110712 (1992-05-01), Kessler et al.
patent: 5602423 (1997-02-01), Jain
patent: 5744394 (1998-04-01), Iguchi et al.
patent: 5827776 (1998-10-01), Bandyopadhyay et al.
patent: 6495917 (2002-12-01), Ellis-Monaghan et al.
patent: 6573538 (2003-06-01), Motsiff et al.
Shue Shau-Lin
Tsai Ming-Hsing
Ackerman Stephen B.
Ho Tu-Tu
Nelms David
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Method for integrating low-K materials in semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for integrating low-K materials in semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for integrating low-K materials in semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3235292