Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-09-25
2004-07-13
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S200000, C365S230010
Reexamination Certificate
active
06762965
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for integrating at least one semiconductor memory device having functional and defective memory cells (an imperfect semiconductor memory device hereinafter) into a data processing apparatus. The invention also relates to a configuration in an imperfect semiconductor memory device that simplifies such an integration.
In the fabrication of today's customary semiconductor memory devices, the large number of individual memory cells in the semiconductor memory device in conjunction with a demanding production process leads to high losses in yield.
The losses in yield are combated nowadays by various redundancy contents that enable a defect-free semiconductor memory device to be emulated outside the memory device, for instance, by providing redundant memory cells that replace defective memory cells by using optically or electrically programmable connecting devices (fuses, antifuses).
Redundancy concepts based on optically programmable connecting devices have hitherto been able to be used only at the wafer level. The effect remains limited to the replacement of defective memory cells that can be identified at the wafer level.
An obstacle to redundancy concepts with electrically programmable connecting devices is an increased production outlay, if for example, production steps outside or in addition to a standard production process of the semiconductor memory device are necessary.
The effect of the customary redundancy concepts is always limited since only limited space for redundant memory cells and for connecting and logic devices required for activating the redundant memory cells is available in the semiconductor memory device. The concepts are insufficient if the number of defective memory cells is very large or if the defective memory cells occur in unfavorably bundled groups.
Moreover, with increasing utilization of redundancy structures, the probability that the redundant structures themselves will have defects rises.
Overall, the effect of previous redundancy concepts remains limited. They increase the production yield only to an inadequate extent even though the absolute number of defective memory cells is small in relation to the total number of memory cells situated in the semiconductor memory device.
Continually rising integration with an increased total number of memory cells per semiconductor memory device and the increasingly more complex production processes mean that the production yield of outwardly defect-free semiconductor memory devices can be expected to continually decrease.
During the production of semiconductor memory devices that outwardly appear to be defect-free, a large number of virtually defect-free semiconductor memory devices (imperfect semiconductor memory devices) with a very small number of defective, irreparable memory cells in relation to the total number of memory cells are obtained. Since customary data processing apparatuses that use semiconductor memory devices have hitherto always presupposed defect-free semiconductor memory devices, such imperfect semiconductor memory devices are unusable at the present time.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method that can be used to integrate semiconductor memory devices, which have defective memory cells that cannot be completely replaced by functional memory cells, into data processing apparatuses. It is likewise an object of the invention to provide a configuration in a semiconductor memory device that will enable the semiconductor memory device to be used with such a method.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for integrating at least one imperfect semiconductor memory device in a data processing apparatus. The method includes steps of: assigning an operating address range to the semiconductor memory device; assigning defect addresses in the operating address range to defective memory cells of the semiconductor memory device; storing the defect addresses in a defect memory; before an instruction processing unit of the data processing apparatus accesses an address in the operating address range, comparing the address to be accessed with the defect addresses; and if the address to be accessed corresponds with one of the defect addresses, recoding the address to be accessed to a replacement address.
In accordance with an added mode of the invention, the method includes steps of: providing the instruction processing unit of the data processing apparatus with a pipeline structure and an address processing unit; using the address processing unit to compare an address contained in a control instruction being shifted through said pipeline structure with the defect addresses, the address to be accessed being the address contained in the control instruction; and if the address contained in the control instruction corresponds with one of the defect addresses, using the address processing unit to recode the address contained in the control instruction into a replacement address before the control instruction is executed.
In accordance with an additional mode of the invention, the method includes steps of: linearizing the operating address range of the semiconductor memory device so that at least one continuous defect-free address range and at least one defect address range are produced in the operating address range; and using the address processing unit to perform testing according to address ranges.
In accordance with another mode of the invention, the method includes: providing at least one semiconductor memory device on a memory module having a non-volatile memory device; and storing defect data, namely the defect addresses or defect address ranges in the non-volatile memory device during a test cycle of the memory module such that the non-volatile memory device defines the defect memory.
In accordance with a further mode of the invention, the method includes steps of: providing non-volatile memory cells in the semiconductor memory device; and storing defect data, namely the defect addresses or defect address ranges in the non-volatile memory cells during a test cycle of the semiconductor memory device.
With the foregoing and other objects in view there is also provided, in accordance with the invention, a configuration in a semiconductor memory device. The configuration includes: a plurality of functional memory cells and a plurality of defective memory cells; a plurality of connection devices; a plurality of external address lines connected to the plurality of the connection devices; a plurality of internal address lines connected to the plurality of the functional memory cells and the plurality of the defective memory cells; and a programmable address decoder for assigning ones of the plurality of the internal address lines connected to the plurality of the functional memory cells to the plurality of the external address lines such that at least one continuous address range is formed from the plurality of the functional memory cells.
In accordance with an added feature of the invention, there is provided, a plurality of redundant memory cells associated with ones of the plurality of the internal address lines; and a standard memory cell array including the plurality of the functional memory cells and the plurality of the defective memory cells. The programmable address decoder is for recoding the ones of the plurality of the internal address lines associated with the plurality of the redundant memory cells to addresses corresponding to the plurality of the defective memory cells to obtain the at least one continuous address range. The addresses corresponding to the plurality of the defective memory cells are in an operating address range.
In accordance with an additional feature of the invention, there is provided, a standard memory cell array including the plurality of the functional memory cells and the plurality of the defective memory cells. The programmable address decoder is also for replacing
Benedix Alexander
Dueregger Reinhard
Ruf Wolfgang
Le Thong Q.
Locher Ralph E.
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