Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-14
2007-08-14
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S116000, C716S030000
Reexamination Certificate
active
11089108
ABSTRACT:
A method and system for integrally checking a chip layout dataset and a package substrate layout dataset for errors are disclosed. The package substrate layout dataset is converted from a first format into a second format in which the chip layout dataset is provided. The chip layout dataset of the second format is combined with the package substrate layout dataset of the second format into a combined dataset. The combined dataset is then checked for errors or design rule violations.
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Chang Shih-Cheng
Chen Kuo-Yin
Cheng Chia-Lin
Wu EJ
Dinh Paul
Duane Morris LLP
Taiwan Semiconductor Manufacturing Co. Ltd.
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