Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-26
2002-12-31
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06502229
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to electronic design automation (EDA) systems for designing integrated circuit devices and in particular, to a method for inserting antenna diodes into an integrated circuit design.
BACKGROUND OF THE INVENTION
During the manufacture of integrated circuit devices, some of the devices may be damaged due to electrostatic charge build-up on the interconnections and their subsequent discharge through the gate oxide of certain transistors during chemical mechanical polishing (CMP) of wafers. A generally accepted practice to relieve transistors against such electrostatic discharge (ESD) is to insert antenna diodes into the IC design so as to provide alternative discharge paths.
Although the insertion of antenna diodes in the integrated circuit design is a simple approach to solving the ESD problem caused by CMP in the manufacturing process, the added components require significant redesign time since the integrated circuit design with the added antenna diodes must be entered at the beginning and proceed through the entire electronic design automation (EDA) process. In addition, the insertion of antenna diodes at this stage of the design requires a full set of new masks or reticles, making the retooling costs particularly high.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method for inserting antenna diodes into an integrated circuit design that minimizes redesign time.
Another object is to provide a method for inserting antenna diodes into an integrated circuit design that minimizes retooling costs.
These and additional objects are accomplished by the various aspects of the invention, wherein briefly stated, one aspect is a method for inserting antenna diodes into an integrated circuit design, comprising: placing design cells in an integrated circuit layout according to a netlist for an integrated circuit design including transistors having gate electrodes; placing filler cells among the design cells in the integrated circuit layout; placing diode cells in the filler cells; routing the design cells according to the netlist so that the diode cells are left unconnected to the design cells; receiving an engineering change order including information of gate electrodes requiring antenna diodes to be coupled to the gate electrodes to reduce electrostatic discharge through the gate electrodes and based upon an analysis of failures of integrated circuit devices generated from the integrated circuit design; determining a corresponding one of the plurality of diode cells for each of the gate electrodes; modifying the netlist to include the corresponding ones of the plurality of diode cells; and routing the design cells and the corresponding ones of the plurality of diode cells according to the modified netlist. Thus, by placing the diode cells in the layout of the original integrated circuit design, only metal mask changes are required in a subsequent redesign to include desired antenna diodes that provide alternative discharge paths for electrostatic discharge during CMP. Also, a re-layout to include the diode cells is not required, thereby reducing redesign time in the EDA process.
Another aspect is a method for inserting antenna diodes into an integrated circuit design having design cells placed according to a netlist, filler cells placed among the design cells, and diodes placed in the filler cells, comprising: receiving information of gate electrodes of the design cells requiring antenna diodes to be coupled to the gate electrodes to reduce electrostatic discharge through the gate electrodes, wherein the information is based upon an analysis of failures of integrated circuit devices generated from the integrated circuit design; determining a corresponding one of the plurality of diode cells for each of the gate electrodes; modifying the netlist to include the corresponding ones of the plurality of diode cells; and routing the design cells and the corresponding ones of the plurality of diode cells according to the modified netlist.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5672895 (1997-09-01), Iida et al.
patent: 6389584 (2002-05-01), Kitahara
patent: 2002/0066067 (2002-05-01), Wang et al.
Chang Xin
Lee Kuo-Chun
Lam Tuan T.
Okumoto Victor H.
Oridus Inc.
Tra Quan
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