Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-07-31
2001-07-31
Booth, Richard (Department: 2812)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000, C438S264000
Reexamination Certificate
active
06268624
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to minimizing the thickness of a gate silicon dioxide at the edges of the gate of an ultra-large scale integration (ULSI) semiconductor device such as a ULSI metal oxide silicon field effect transistor (MOSFET), and more particularly to methods for inhibiting a local increase in the tunneling distance in the tunnel oxide at the gate edge of a floating gate EEPROM, or flash memory device.
BACKGROUND OF THE INVENTION
Semiconductor chips are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate stack on a Silicon substrate, and then forming a source region and a drain region in the substrate beneath the gate stack by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate stack is insulated from the substrate by a thin gate oxide layer, also referred to as a “tunnel oxide” layer, with small portions of the source and drain regions extending toward and virtually under the tunnel oxide layer.
Between the source and drain regions and under the tunnel oxide layer is a channel region, a portion of which is doped. The doped portion of the channel region typically is doped early in the fabrication process, with the channel dopant usually being implanted during the steps of forming the gate and source and drain regions. This generally-described structure cooperates to function as a transistor.
To promote proper transistor functioning, the overall tunnel oxide thickness is established in part by reliability concerns such as data retention, endurance, and so on; however, the edges of the tunnel oxide can grow during source/drain formation and other steps used to seal the floating gate to prevent unintentional transport of electrons out of the gate, such sealing being required because the presence of these electrons determines whether the device is programmed.
Excessive growth of the tunnel oxide at the gate edges, however, reduces the electric field that must be used to erase the device, i.e., to transport electrons from the floating gate to one of the source/drain regions using Fowler-Nordheim tunneling. This in turn undesirably reduces the speed of the erase operation, because Fowler-Nordheim tunneling varies exponentially with the electric field across the oxide layer, and the erase speed, as understood herein, varies strongly as a function of the tunnel oxide thickness. U.S. Pat. No. 5,077,691, owned by the same assignee as is the present invention and incorporated herein by reference, sets forth added details of flash EEPROM voltage erase operations.
It happens that the erase current takes a path through the end regions of the tunnel oxide layer that are directly above the source and drain.
FIG. 1
shows a tunnel oxide layer
1
with end regions
2
,
3
below a floating gate
4
of a transistor
5
. It further happens that although the end regions of the tunnel oxide layer are initially formed uniformly thin along with the remainder of the layer, during oxidation steps subsequent to gate formation such as, e.g., formation of the source and drain regions, as stated above we have recognized that oxygen can diffuse into the end regions of the tunnel oxide layer, causing the end regions to grow thicker. The resulting upturned upper edges of the end regions, shown at
6
and
7
in
FIG. 1
, resemble what is colloquially referred to herein as a “bird's beak” profile, “lateral oxide encroachment”, and “gate edge lifting”. In any case, the thicker end regions inhibit erase current and cause the erase current to be concentrated through thinner portions of the gate edge lifting profile, thereby decreasing floating gate erase uniformity and overall chip reliability. The present invention recognizes the above-noted “gate edge lifting” problem and provides the solutions set forth below.
BRIEF SUMMARY OF THE INVENTION
A method for establishing at least one transistor on a semiconductor device includes providing a semiconductor substrate and establishing at least one tunnel oxide layer on the substrate. The method further includes forming at least one transistor gate stack including the tunnel oxide layer. In accordance with the present invention, at least one barrier film is established on the gate stack, after which source and drain regions are established in the substrate. With this invention, the barrier film inhibits diffusion of oxygen into the edge of the tunnel oxide layer as, e.g., the source and drain regions are established.
In a preferred embodiment, the barrier film has a thickness of between twenty Angstroms and two hundred Angstroms (20 Å-200 Å), and more preferably the barrier film has a thickness of between fifty Angstroms and one hundred fifty Angstroms (50 Å-150 Å). As set forth below, the barrier film can be made of oxide such as Silicon dioxide (SiO
2
), Silicon oxynitride (SiON), or stoichiometric silicon nitride (Si
3
N
4
), and the film can be established by growing it at a temperature of between seven hundred fifty degrees Celsius and one thousand fifty degrees Celsius (750° C.-1050° C.) or by depositing it using high temperature oxide (HTO) chemical vapor deposition at between 350° C.-900° C., or by using chemical vapor deposition (CVD), PCVD, or PECVD.
In addition, the method can include establishing a second barrier film over the first barrier film. One or both of the barrier films can be removed after establishing the source and drain regions.
In another aspect, a method for making an ultra-large scale integration (ULSI) semiconductor device includes providing a semiconductor substrate and establishing a transistor gate on a tunnel oxide layer that has at least one exposed side surface extending between the transistor gate and the substrate. Furthermore, the present method includes forming source and drain regions in the substrate beneath the tunnel oxide layer. As intended by present principles, during the forming act, oxidation of the exposed side surface of the tunnel oxide layer is inhibited.
In yet another aspect, a semiconductor device includes a transistor gate on a semiconductor substrate and a tunnel oxide layer sandwiched between the gate and the substrate. The tunnel oxide layer defines an edge extending between the substrate and the gate. A source region and a drain region are in the substrate below the gate, and at least one barrier film covers at least the edge of the tunnel oxide layer.
Other features of the present invention are disclosed or apparent in the section entitled “DETAILED DESCRIPTION OF THE INVENTION”.
REFERENCES:
patent: 5384272 (1995-01-01), Ibok et al.
patent: 5424232 (1995-06-01), Yamauchi
patent: 5460992 (1995-10-01), Hasegawa
patent: 5554551 (1996-09-01), Hong
patent: 5633184 (1997-05-01), Tamura et al.
Haddad Sameer S.
Huster Carl R.
Pham Tuan Duc
Ramsbey Mark T.
Sobek Daniel
Advanced Micro Devices , Inc.
Booth Richard
LaRiviere Grubman & Payne, LLP
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