Method for inhibiting thrashing in a multi-level non-blocking ca

Details Method for inhibiting thrashing in a multi-level non-blocking ca Method for inhibiting thrashing in a multi-level non-blocking ca

1997-06-25

2000-11-28

Yoo, Do Hyun

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711140, 711167, G06F 1208

Patent

active

06154812&

ABSTRACT:
A data cache unit associated with a processor, the data cache unit including a first non-blocking cache receiving a data access from a device in the processor. A second non-blocking cache is coupled to the first non-blocking cache to service misses in the first non-blocking cache. A data return path coupled to the second non-blocking cache couples data returning from the second non-blocking cache to both the first non-blocking cache and the device generating the access to the first non-blocking cache.

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