Method for increasing the equivalent computational precision...

Details Method for increasing the equivalent computational precision... Method for increasing the equivalent computational precision...

2000-04-06

2003-03-18

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S001000, C711S206000, C711S221000

Reexamination Certificate

active

06535952

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a method for increasing the equivalent computational precision in an analog associative memory.
BACKGROUND OF THE INVENTION
It is known that analog techniques can lead to highly efficient computing systems when used for the appropriate applications.
The use of an associative analog memory in which both the stored memory rows and the inputs consist of analog vectors (with a 5-bit equivalent precision) leads to architectures which can be highly efficient both in terms of high density and in terms of low energy consumption.
The operation of an associative memory or content-addressable memory, is roughly the opposite of a random-access memory. When a partial or complete data vector is presented to the associative memory, the memory should return the row address of the internally stored data vector that best “matches” the data vector in input to the associative memory.
An analog associative memory is based on programmable nonlinear capacitors implemented with flash-EEPROM technology. Each device in the memory array can store an analog value with a maximum equivalent precision of 5 bits and, when an analog input is supplied, it can compute the absolute value of the difference between the value stored in the device and the value in input. Analog associative memories have a high capacity for the parallel processing of a large amount of data and the ability to provide inexact recognition, so as to be suitable for pattern-matching processing.
In an analog associative memory, the recognition of a pattern occurs, as mentioned, by performing a comparison of the data by means of differences between voltages stored in the flash devices, at a level of resolution of no more than 5 bits. The inherent physical limitations of the device being considered in fact do not allow one to achieve higher data resolutions.
Accordingly, the drawback of conventional analog associative memories is that their range of utilization is limited to applications which do not require high resolution of the data to be handled. For example, when using an analog associative memory as an image compressor, the 5-bit resolution is barely sufficient to ensure an image of reasonable quality.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides a method for increasing the equivalent computational precision in an analog associative memory which allows one to maintain intact the initial precision of each individual device of the memory.
The method increases the equivalent computational precision in an analog associative memory in which the data in the memory are represented in a different manner, maintaining the computational simplicity characteristics of the associative memory and at the same time increasing the obtainable resolution. The method does not entail physical changes to the memory arc, is highly reliable, and is relatively simple to provide at competitive costs.
The method comprises the steps of:
determining, for an associative memory, the difference between the bit precision that is required in order to represent a given number in said memory and the bit precision that can be represented in said memory, which is dictated by the inherent characteristics of said memory;
determining, on the basis of said difference, the number of devices of said memory required in order to represent said given number with the required bit precision; and
dividing said given number over said number of devices of said memory, determining a base value to be loaded into said number of devices and a remainder which indicates a subset of said number of devices of the memory over which said remainder is to be divided.


REFERENCES:
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Lee et al., “Analog Floating-Gate Synapses for General-Purpose VLSI Neural Comptation,” IEEE, pp 654-658, Jun. 1991.*
Andreou et al., “Neural Architectures for Smart Memories in Analog VLSI,” IEEE, pp 671-676, Aug. 1988.

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