Method for increasing retention time in DRAM

Details Method for increasing retention time in DRAM Method for increasing retention time in DRAM

2007-03-12

2010-02-16

Nguyen, Dang T (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S203000, C365S104000

Reexamination Certificate

active

07663908

ABSTRACT:
The disclosure generally relates to a method and apparatus for decreasing the frequency of refreshing a memory cell in communication with a word line and a bit line. A method according to one embodiment includes: providing a DRAM circuit having a memory cell, a sense amplifier including a pre-charge circuit connected to a first voltage source and a back-to-back inverter including a first NMOS transistor having a source, a second NMOS transistor having a source, a first PMOS transistor having a source and a second PMOS transistor having a source; maintaining the voltage of the sources of the first and second PMOS transistors at a first voltage during normal operation; and raising the voltage of the sources of the first and second PMOS transistors from the first voltage to a second voltage during a refresh operation.

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patent: 2002045959 (2002-06-01), None

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