Method for increasing manufacturability of a circuit layout

Details Method for increasing manufacturability of a circuit layout Method for increasing manufacturability of a circuit layout

2006-05-19

2009-02-03

Garbowski, Leigh Marie (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07487492

ABSTRACT:
According to one exemplary embodiment, a method for increasing manufacturability of a circuit layer includes determining a threshold value for at least one image property from a repetitive section of the circuit layout. According to this embodiment, the method further includes performing a simulated lithographic process using the circuit layout to determine a number of simulated values of the at least one image property for a non-repetitive section of the circuit layout. The method further includes comparing each of the simulated values with the threshold value to determine printability of the non-repetitive section of the circuit layout prior to lithographically printing the circuit layout on a wafer. The method further includes modifying the non-repetitive section of the circuit layout if the threshold value is greater than at least one of the simulated values. By modifying the non-repetitive section of the circuit layout, manufacturability of the circuit layout can be increased.

REFERENCES:
patent: 6775818 (2004-08-01), Taravade et al.
patent: 6907596 (2005-06-01), Kobayashi et al.
patent: 7340706 (2008-03-01), Golubtsov et al.
patent: 2007/0044049 (2007-02-01), Adams et al.

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