Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating
Reexamination Certificate
2011-03-29
2011-03-29
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Testing or evaluating
Reexamination Certificate
active
07917883
ABSTRACT:
Methods, software, and apparatus for providing a netlist for simulation that includes one or more parameters that are determined by one or more pattern dependent effects. One particular embodiment of the present invention receives a layout of a circuit including one or more MOSFET transistors. For one or more of the MOSFET transistors, spacing between transistors is measured using the received layout and a pattern dependent parameter is determined. This parameter modifies the length of the gate that is used in simulation. In other embodiments, other pattern dependent effects can be used to determine the values of one or more parameters. These parameters may be used to modify gate length, emitter size, resistor width, or other device characteristics.
REFERENCES:
patent: 6425117 (2002-07-01), Pasch et al.
patent: 6898561 (2005-05-01), Liu et al.
patent: 6978229 (2005-12-01), Saxena et al.
patent: 2004/0044511 (2004-03-01), Sekido et al.
patent: 2004/0153986 (2004-08-01), Sahara et al.
patent: 2005/0076316 (2005-04-01), Pierrat et al.
patent: 2005/0216873 (2005-09-01), Singh et al.
Altera Corporation
Chiang Jack
Memula Suresh
Ropes & Gray LLP
LandOfFree
Method for incorporating pattern dependent effects in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for incorporating pattern dependent effects in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for incorporating pattern dependent effects in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2673777