Method for in-system programming of serially configured EEPROMS

Details Method for in-system programming of serially configured EEPROMS Method for in-system programming of serially configured EEPROMS

1999-11-30

2000-10-24

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

36518501, G11C 2900

Patent

active

061377384

ABSTRACT:
A method for programming an electrically erasable programmable read only memory (EEPROM) while mounted on a printed circuit board. The EEPROM is used as a memory storage device for a field programmable gate array (FPGA), which is mounted on the printed circuit board. The board and FPGA have a joint test action group (JTAG) test interface. The FPGA contains a test access port (TAP) and user defined internal scan registers. The method includes providing a connection between the TAP of the FPGA and the EEPROM. Data is provided to the internal scan data registers of the FPGA via the JTAG test interface. Data is transferred via the internal scan data registers to the EEPROM without interrupting operation of the FPGA.

REFERENCES:
patent: 5270977 (1993-12-01), Iwamoto
patent: 5471430 (1995-11-01), Sawada et al.

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