Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-08-08
2003-12-02
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S726000, C438S734000, C438S739000
Reexamination Certificate
active
06656850
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the device fabrication arts. It finds particular application in the removal of titanium-containing sidewalls which develop during formation of metal-oxide-metal capacitors, and will be described with particular reference thereto.
BACKGROUND OF THE INVENTION
Capacitors are widely used in integrated circuits. Metal-oxide-metal (MOM) capacitors are formed on an insulative support, such as a silicon wafer, with a field oxide, such as silicon dioxide, coating one surface. A conductive layer, such as a layer of titanium nitride or other conductive material, is deposited on the insulated support to form a first conductive electrode. A dielectric film is then deposited on the electrode material. The dielectric material may comprise a layer of silicon dioxide, or other dielectric material, or a stack of several layers of different dielectric materials, such as silicon dioxide and silicon nitride. The dielectric film is patterned with a photoresist material to define the capacitor feature. The unwanted silicon dioxide around the capacitor is then etched to expose the titanium nitride electrode beneath. Finally, the photoresist material is stripped from the dielectric material and a second layer of conductive material, such as aluminum, is deposited on the upper surface of the dielectric film to define a second electrode.
The etching process for removal of unwanted dielectric material is typically carried out in a plasma etching tool, such as a reactive ion etch (RIE) reactor. An anisotropic etch is often used to define the shape of the capacitor feature. During the etching process, however, titanium-containing sidewalls develop at the edges of the capacitor feature. These sidewalls form as a result of sputtering of the titanium nitride layer during the necessary over-etch. Unless removed, the titanium-containing sidewalls can short the electrodes of plates of the capacitor. Additionally, if not removed, the sidewalls have been found to cause corrosion of the aluminum top layer of the capacitor, leading to degradation of the capacitor functions and can reduce yields.
The sidewalls are not easily removed during conventional solvent cleaning processes. Additionally, solvents used to remove the sidewalls often have high levels of mobile ion contaminants (i.e., Na
+
, K
+
). If the contaminants become absorbed by the device, they may travel through the various layers and cause electrical device defects and degradation in the overall performance and yield of the device. Wet chemicals, such as BOE (buffered oxide etch, a mixture of NH
4
F and HF in solution) mixed with ethylene glycol or NE
14
(a mixture of dimethylacetamide, NH
4
F, and water), that contain fluorine, will etch the capacitor dielectric, and therefore are unsuitable for removing the sidewalls.
An alternative method of removing the unwanted dielectric material is to pattern the dielectric in an isotropic plasma etch. The isotropic etch process does not result in excessive sidewalls. This approach can produce a well defined capacitor dielectric if the dielectric material is a single material, such as silicon dioxide. However, the technique is not readily suitable for use when the dielectric is a stack of different dielectric materials, such as silicon dioxide and silicon nitride layers, commonly referred to as an oxide-nitride-oxide (ONO) stack. The silicon nitride layers in the stack etch away much faster than the silicon dioxide layers in this type of etching process, and notching or undercutting of the nitride layers can result. This, in turn, can result in shorting of the capacitor plates.
Additionally, the isotropic etching techniques that use ceramic plasma tubes have severe particle problems when used for the long process times needed to pattern silicon dioxide and similar dielectric materials.
What is needed, therefore, is method of patterning a dielectric layer which overcomes the above-referenced problems, and others.
SUMMARY OF THE INVENTION
In accordance with one aspect of the present invention, a method of fabricating an integrated circuit metal-oxide-metal capacitor is provided. The method includes forming a first electrically-conductive layer on an electrically insulating support and depositing a dielectric film on the first conductive layer. A portion of the dielectric film is then etched. The method further includes etching sidewalls from a remaining portion of the dielectric film. The sidewalls are formed during etching of the dielectric due to over-etching of the first conductive layer.
In accordance with another aspect of the present invention, a method for etching a patterned dielectric film comprises depositing a dielectric film on an electrically-conductive layer and patterning the dielectric film with a mask material. Unmasked regions of the dielectric film are anisotropically etched with a first plasma in a plasma reactor. Sidewalls are etched in the plasma reactor with a second plasma which is substantially isotropic in character. The sidewalls are formed on masked regions of the dielectric film during the anisotropic etching step, and comprise material sputtered from the electrically conductive layer.
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Harris Edward Belden
Layadi Nace
Molloy Simon J.
Sen Sidhartha
Agere Systems Inc.
Jr. Carl Whitehead
Pham Thanhha
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