Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-11-21
2004-11-09
Dang, Phuc T (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S708000, C438S735000
Reexamination Certificate
active
06815345
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to in-line monitoring of via/contact etching process in semiconductor device fabrication by using a scanning electron microscope (SEM), and more particularly to methods and devices for determining whether via/contact holes are over or under etched in the process of fabricating a semiconductor device.
2. Description of the Prior Art
Very large-scale integrated (VLSI) circuits rely on via/contact holes (as well as trenches) for electrically interconnecting devices of different layers, interconnecting a layer to an underlying substrate, or interconnecting a layer to another layer. The electrical defects associated with the deep (high aspect ratio) sub-micron via/contact holes takes up a significant parts of the total yield loss as the current technology approaches to the 0.1 &mgr;m node. It is, therefore, essential to ensure that the etching process for creating such via/contact holes are optimized and in-line controlled within the process window, so that the potential via/contact failure due to either process parameters shifting or wafer-to-wafer dielectric thickness variation can be identified and avoided in the early steps.
Because of the nonuniformity in the etch rate, and the fact that the-film itself may be of nonuniform thickness across the wafer or from wafer to wafer, a certain amount of over-etching is done to ensure that complete etching is achieved everywhere on the wafer, and appropriate electrical contact is obtained. This is often 10-20% over-etching in terms of time past the endpoint point. Even more over-etching (as much as 50%) may be required when anisotropic processing is done over non-planar topography. However, as the technology shrinks into the 0.10 &mgr;m mode, the thickness of over-etch margins have dropped drastically. Excessive over-etch of contact holes will cause the thin metal silicide layer on top of a drain/source region to be diminished due to the limited selectivity of the etch process. Also important, there is high probability that the contact penetrates the shallow pn-junction beneath the drain/source that leads to high leakage current. For via etch processes aiming at open dielectric barriers over the lower metal level, it is also necessary to avoid excessive dielectric barrier over-etch; otherwise, copper is exposed and sputtered during the over-etch step, potentially compromising device reliability.
The integrity of via/contacts can be validated by measuring the resistance of long chains connecting thousands of vias/contacts in series with each other and located in the scribe lines or in test chips on the wafer. These via/contact chains pass over various topographies. A current is forced through these long chains, and the measured voltage is a measure of the average contact resistance. These structures are used to monitor the via/contact as a function al processing conditions and structures, and to measure lot-to-lot variation. A high value of resistance in these structures could indicate a problem with under-etch, over-etch, and/or etch residue, but may also be causes of poor metal deposition, voids in contact region, or other problems incurred in subsequent processes. In addition, this test cannot be performed before completion of the conductive wiring chain. This increases the manufacturing cost.
An electron beam inspection system, or in its simplest form, a conventional scanning electron microscope (SEM), has been proven to be a powerful tool for imaging electrical defects such as via/contact short. As the primary electron beam scans over the inspection area, low energy secondary electrons (SE) (~5 eV) will be generated from the surface and collected by the SE detector to form an image. Due to the differences in SE yields of the involved materials or the abnormal electrical conductivity of the defect portions, the inspected surface will be unevenly charged positively and/or negatively. Negatively charged surfaces tends to produce more SE to the signal detector, thus its appearance is relatively brighter, while a positively charged surface attracts more SE and thus appears relatively darker. This is the so-called voltage contrast (VC). VC can be used roughly to divide via/contact holes into the categories of under-etch or over-etch. However, it lacks the sensitivity to the level of under-etch or over-etch, thus is not suitable for process monitoring.
SUMMARY OF THE INVENTION
An objective of this invention, therefore, is to provide a method and test structures to monitor the via/contact etching uniformity over a dielectric layer of a wafer.
Another objective of this invention is to provide a method and test structures to monitor the process variation due to etching parameters shifting and/or dielectric layer thickness variation from wafer-to-wafer or lot-to-lot.
A further objective of the present invention is to provide a method and test structures to estimate the amount of over-etch or under-etch in the actual device region with respect to the just-etch.
In accordance with the above-described objects and those that will be mentioned and will become apparent below, a test structure for monitoring the via/contact holes includes the provision of via/contact holes of different sizes and densities formed into a dielectric layer for making contact to the buried conductive layer or active regions such as source/drain. The thickness of the dielectric layer as well as its topography resembles that required in the functional dies for making actual devices.
FIG. 1
depicts one of such layout as an array with density varying along columns
101
and hole size varying along rows
102
. The test structures may be placed on the semiconductor wafers as “drop-ins,” which are located where functional dies would normally be placed. Or they can be placed in wafer scribe lines, which are lines between functional dies defining diamond saw cuts that separate finished devices. The via/contact holes in the test structure, formed simultaneously with those in the functional die, will be etched to different levels as the result of the microloading effect or RIE “lag”. With reference to the related patent application referenced above, voltage contrast of these holes will reverse at certain beam conditions from bright to dark if the thickness of under-etch remains over a threshold value at a certain primary beam energy and current, as shown in FIG.
2
. Curve
201
depicts the SE signals (normalized to background signal) originating from the via/contact hole bottom as a function of thickness of remains or recesses with respect to just-etch. Point
202
corresponds to the threshold thickness across which the contrast of the hole reverses. If the test structure is properly designed in such a way that the etching variations inside the hole ranges from under-etch to excessive over-etch, for instance, from −150 Å (over-etch) to 100 Å (under-etch), the VC contrast of these holes will experience a transition from bright to dark. For the test structure in
FIG. 1
, the corresponding VC image may have a similar appearance as shown in FIG.
3
. Via/contact holes at the lower-right corner are of smaller sizes and relatively higher densities, thus turn up brighter due to the relatively slow etching rate associated with microloading effects, while for those at the upper-left corner having relatively larger holes and lower density, turn out to be darker as over-etching commonly happens. There is a narrow transition region lying between the upper-left and lower-right corners, at which image signals are so sensitive to the actual remains that holes may appear white or dark, depends on the randomly thickness variation.
The foregoing VC transition image characterizes the etching process as its size and location should are generally fixed for a given process. Proper image processing, for instance, by subtracting two similar images of the adjacent test structures, may highlight the VC transition portion in the resulting image. This resulting image can be regarded as a “fingerprint” i
Chen Zhongwei
Jau Jack
Yeh Chang-Chun (Roland)
Zhao Yan
Dang Phuc T
Hermes-Microvision (Taiwan) Inc.
Townsend and Townsend / and Crew LLP
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