Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-08-31
2001-10-16
Phan, Trong (Department: 2818)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06305004
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to VLSI circuit design, and more specifically to a method for performing automatic wiring of an integrated circuit chip, module or card.
BACKGROUND OF THE INVENTION
Automatic routing of VLSI chips, modules or cards can be accomplished by a variety of methods, many of which have been known and studied for at least 20 years. It is acknowledged by practitioners that automatic routing consists of two stages: a Global Routing, which produces rough locations of wires, and a Detailed Routing, which takes the results of the global routing to generate detailed locations and layers for wiring the chip.
Automatic routing has been enhanced by taking into consideration certain relevant factors which improve the electrical characteristics of the package being wired. Some of these techniques have been described in the literature, examples of which are listed below:
S. Y. Kuo, “YOR: an yield optimizing routing algorithm by minimizing critical areas and vias,” published in the IEEE Transactions on CAD, Vol. 12, No. 9, pp 1303-1311, September 1993;
Z. Chen and I. Koren, “Layer assignment for yield enhancement”, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, November 1995, pp 173-180;
Pitaksanonkul et. al., “DTR: A Defect Tolerant Routing Algorithm”, Proceedings of 26st Design Automation Conference, pp 795-798, 1989;
A. Venkataraman, H. H. Chen and I. Koren, “Yield enhanced routing for high-performance VLSI designs”, Proceedings of SPIE Conference on Microelectronic Manufacturing Yield, Reliability, and Failure Analysis, pp 50-60, October 1-2, 1997;
T. G. Waring, G. A. Allan and A. J. Walton, “Integration of DFM Techniques and Design Automation”, Proceedings IEEE International Conference on Defect and Fault Tolerance in VLSI Systems, pp 59-67, 1996; and
M. Lorenzetti, “The Effect of Channel Router Algorithms on Chip Yield,” Proceedings of International Workshop on Layout Synthesis, May 1990.
A conventional Detailed Routing can be achieved by following one of two approaches:
1) Channel routing, wherein the router connects all the nets, allowing for an increase of the area taken by the wiring to achieve all the connections, and
2) Area routing, wherein the router is given a fixed area to connect all the nets.
The above listed references generally describe various methods which apply exclusively to channel routing, (as opposed to area routing). Channel routing techniques are mostly interesting as a research tool but are seldom used in practice, mainly because of the aforementioned wiring versus area tradeoff.
Within the context of area routing, attempts have been made to improve yield while wiring a chip, module, and the like. Such an approach is described in an article by:
E. P. Huijbregts, H. Xue and J. A. G. Jess, “Routing for Reliable Manufacturing”, IEEE Transactions on Semiconductor Manufacturing, vol. 8, pp 188-194, 1995.
The above mentioned article by E. P. Huijbregts et al., is of particular interest since formulae are developed that measure yield effects as a function of wire length, common run length, and wiring crossing areas. These formulae are then combined with the traditional steiner tree routing objective (which is the same objective used for maze routing), using a scaled weight (or cost) proportional to the sparsity of the circuit. Using these formulae, the maze routing expansion method is modified to include the region surrounding the wire to compute the cost of the wire. Yet, the method described by E. P. Huijbregts et al. includes complex formulae to derive the weights which control the maze runner. This approach suffers from certain fundamental limitations, such as the applicability of these formulae which depend on assumptions made about the manufacturing model and the design which are not generally applicable. Further, the method requires modifying the core of the maze router, which results in a severe performance penalty.
OBJECTS OF THE INVENTION
Accordingly, it is an object of the invention to efficiently and automatically wire a VLSI integrated circuit (IC) chip or module.
It is another object of the invention to employ area routing (also referred as maze routing), wherein the router is given a fixed area to connect all the nets.
It is a more particular object of the invention to wire the chip and the like, while optimizing yield, reducing capacitance and avoiding coupled noise.
It is yet another object of the invention to maintain the maze routing unaltered by varying the weights used by the method and procedure (i.e, the cost) by which these weights are created.
It is still another object of the invention to make it possible to use any maze router without modifying its function.
It is a further object of the invention to ensure that the run time of the maze router remains constant, particularly since any time penalty is usually caused by updates to the weights.
It is still a further object of the invention to derive the maze routing weights in a systematic fashion, while accounting explicitly for the ultimate stated goal, i.e., yield improvement, as well as capacitance and/or noise reduction.
It is yet another object of the invention to employ the area routing method known as maze routing with rip-up and re-route.
REFERENCES:
patent: 4615011 (1986-09-01), Linsker
patent: 5483461 (1996-01-01), Lee et al.
patent: 5644500 (1997-07-01), Miura et al.
Chen, et al. “Layer Assignment for Yield Enhancement” pp. 173-180. 1995.
A. Pitaksanonkul, et al. “DTR: A Defect-Tolerant Routing Algorithm” 26thACM/IEEE Design Automation Conference pp. 795-798. 1989 (no date).
Xue, et al. “Routing for Manufacturability” pp. 1-5.
Kuo, et al. “YOR: A Yield-Optimizing Routing Algorithm by Minimizing Critical Areas and Vias” IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. vol. 12 No. 9 Sep. 1993 (no date).
A. Venkataraman, et al. “Yield Enhanced Routing for High-Performance VLSI Designs” pp. 1-10.
Waring, et al. “Integration of DFM Techniques and Design Automation” pp. 59-67. 1996 (no date).
Doyle Gary
Honsinger Philip
Lovejoy Steven
Meiley Charles
Starkey Gorden
International Business Machines - Corporation
Phan Trong
Schnurmann H. Daniel
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