Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-04-05
2001-04-10
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S598000, C438S618000, C438S622000, C438S631000, C430S312000
Reexamination Certificate
active
06214722
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88103922, filed Mar. 15, 1999.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing an interconnect.
2. Description of the Related Art
Due to the increasingly high integration of ICs, chips simply cannot provide sufficient area for manufacturing interconnections. Therefore, in accord with the increased interconnect manufacturing requirements of miniaturized MOS transistors, it is increasingly necessary for IC manufacturing to adopt a design with more than two metal layers. In particular, a number of multi-function products, such as microprocessors, may even require 4 or 5 metal layers to complete the internal connections thereof. Generally, an inter-metal dielectric (IMD) layer is used to isolate electrically two adjacent metal layers from each other.
In order to perform an interconnection more easily and to transfer the pattern more precisely, it is important to have a wafer with an even topography. Since the probability of inaccuracy of the alignment system can be reduced by using a wafer with a relatively even topography, the fine pattern can be transferred more accurately.
FIGS. 1A through 1B
are schematic, cross-sectional views of the conventional pattern transfer process.
As shown in
FIG. 1A
, a substrate having a conductive layer
120
, wires
120
a
and
120
b
and a insulating layer
122
formed thereon is provided. A dotted line I—I divides a wafer (not shown) into two parts. One side of the dotted line I—I, denoted as region
116
, is the interior region of the wafer, wherein the interior region has effective dies. The other side of the dotted line I—I, denoted as region
118
, is the edge region of the wafer. The dies in the region
118
are incompletely formed, so that the region
118
is a region having ineffective dies. Since the distribution density of the conductive layer
120
is higher than that of the wires
120
a
and
120
b
, the ability of portions of the insulating layer
122
in the region
118
to resist the planarization step is higher than that in the region
116
. Hence, portions of the insulating layer
122
in the region
118
are thicker than the portions of the insulating layer
122
in the region
116
after chemical-mechanical polishing (CMP). Because the region
118
is higher than the region
116
, a sloped surface
124
of the insulating layer
122
above the wire
120
a
is shown in the region
116
adjacent to the region
118
. In highly integrated ICs, the interconnection is more than one layer, so that the step height between the regions
118
and
116
is increasingly larger.
As shown in
FIG. 1B
, a photoresist
128
is formed on the insulating layer
122
. Photolithography is performed to form openings
130
a
and
130
b
in the photoresist
128
, respectively aligned with the wires
120
a
and
120
b
. The opening
130
b
may be formed to expose the underlying dielectric layer
122
since the photoresist
128
is within the range of depth of focus (DOF). The DOF range is from the optimum focus BF to the maximum AF at both sides of the optimum focus BF. As the portion of the photoresist
128
over the wire
120
a
is higher and beyond the DOF, so that an error occurs for the photolithography process. As a consequence, the opening
130
a
fails to expose by the dielectric layer
122
. This is called scumming. Additionally, the defocusing happens since a conductive layer subsequently formed on the region
118
is relatively high and beyond the DOF. Therefore, the conductive layer caves.
Generally, the step height of the photoresist caused by the profile of only one conductive layer is about 1000-3000 angstroms, which is an allowable error range. In other words, difference between the photoresist
128
in the region
118
and in the region
116
is about 1000-3000 angstroms. However, the step height increases as the number of the conductive layers increases. Therefore, the step height is more than 6000-7000 angstroms beyond the tolerable range. Hence, the scumming easily happened and it is difficult to accurately transfer a fine pattern from the photomask to the wafer.
SUMMARY OF THE INVENTION
The invention provides a method of manufacturing an interconnect. By using the invention, the problem of scumming can be overcome and the throughput can be greatly enhanced.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing an interconnect. A wafer having an edge region and an interior region is provided. An insulating layer is formed on the wafer. An opening penetrating through the insulating layer in the interior region is formed and a portion of the insulating layer is removed to expose the surface of the wafer in the edge region, simultaneously. A conductive layer is formed on the insulating layer and the exposed surface of the wafer exposed by the insulating layer and fills the opening. The conductive layer is patterned to form a wire in the opening. Since the insulating layer in the edge region of the wafer is lower than that in the interior region of the wafer and the sloped surface of the insulating layer is in the edge region, a fine pattern can be more accurately transferred from the photomask into the insulating layer. The problem of scumming can be also overcome. Moreover, the throughput can be greatly enhanced by using the invention.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5459340 (1995-10-01), Anderson et al.
patent: 5767011 (1998-06-01), Yao et al.
patent: 5783482 (1998-07-01), Lee et al.
patent: 5966628 (1999-10-01), Wei et al.
patent: 5972798 (1999-10-01), Jang et al.
Hsu Bill
Lin Chien-Chih
Peng Nien-Tsu
Bowers Charles
Huang Jiawei
J.C.Patents
Smoot Stephen W.
United Microelectronics Corp.
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