Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-03-29
2008-08-05
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C700S097000, C700S110000, C703S002000, C703S014000
Reexamination Certificate
active
07409668
ABSTRACT:
A method is for controlling an impedance of a via of a printed circuit board. The Via is connected with a trace and includes a drill hole, a pad and an anti-pad. The method includes steps of: building a math model; testing whether an impedance of the via matching with an impedance of the trace; analyzing the impedance of the via if passing the testing; and adjusting parameters of the pad, the anti-pad, and the drill hole if fails testing, and returning to the simulating step, till impedance matching achieved. The method which can efficiently keep signals integrality and increase signal transmission speed.
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Hong-Guan Low, Mahadevan K. Iyer, Ban-Leong Ooi, Mook-Seng Leong, “Via Design Optimisation For High Speed Device Packaging”, 1998 IEEE/CPMT Electronics Packaging Technology Conference, 1998, pp. 112-118, Singapore.
Li Chuang-Bing
Lin Yu-Hsu
Yeh Shang-Tsang
Hon Hai Precision Industry Co. Ltd.
Hong Fu Jin Precision Industry ( Shenzhen) Co., Ltd.
Kik Phallaka
Morris Manning & Martin LLP
Tingkang Xia, Esq. Tim
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