Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
1999-08-12
2001-07-17
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S719000, C438S723000, C438S724000, C438S743000, C438S744000
Reexamination Certificate
active
06261966
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a process for electrically isolating semiconductor devices and components in integrated circuits. In particular, the invention is a process for forming a trench isolation which can prevent the leakage problem induced by a wedge shaped insulating layer inside the trench.
BACKGROUND OF THE INVENTION
Modern isolation techniques have used trenches etched into the semiconductor substrate. A common trench isolation approach involves variations on the basic sequence of etching the trench, forming a thin oxide layer on the trench sidewalls, then filling the trench with polycrystalline silicon. For example, U.S. Pat. No. 4,104,086 to Bondur et al. uses tapered trench sidewalls to control the depth of any voids in relation to the substrate surface and forms a composite dielectric inside the trench.
U.S. pat. No. 4,356,211 to Riseman also forms an oxide layer in the trench, but then deposits a conformal layer of polycrystalline silicon. The polycrystalline silicon is implanted so that differential oxidation of the polycrystalline silicon near the surface of the trench encloses the trench and the underlying voids.
U.S. pat. No. 4,835,115 issued on May 30, 1989, to Eklund for “Method for forming oxide capped trench isolation” teaches a method for preventing the leakage problem from overlying contact to the polycrystalline silicon plug by forming an oxide-capped trench isolation.
The trench isolation provided in these examples use a polycrystalline silicon plug within the trench to overcome the problems of localized stress from trench arising due to the dissimilarity of the coefficients of thermal expansion of the substrate (e.g. silicon) to the insulator (e.g. silicon dioxide), as well as the stress from the formation of a filling oxide. The polycrystalline silicon plug filling the trench after formation of the sidewall dielectrics serves to minimize the stress, as it minimizes the formation and volume of the oxide within the trench.
However, it is beneficial to provide a thick dielectric layer over the top of the polycrystalline silicon plug in the trench in order to prevent from the leakage from the overlying layer to the polycrystalline silicon plug caused by over-etching, e.g. the contact via, into polycrystalline silicon plug.
Variations on the common approach of filling the trench with polycrystalline silicon, planarizing the polycrystalline silicon by an etch back or polishing, and oxidizing the polycrystalline silicon to form a capping oxide layer are disclosed in Goto et al. An oxide layer is grown over the trench after it has been filled with a polycrystalline silicon plug. While resulting in a thicker oxide over the filled trench, such oxide growth creates significant stress on the trench structure during its growth. This stress results from the growth of oxide at the sidewalls at the trench and at the plug, near the top of the trench. In effect, a wedge of oxide is attempting to grow in the space between the plug and the substrate, such space already containing a sidewall oxide, resulting in similar stress problems as that encountered at the bird's beak of local oxidation of silicon (LOCOS) isolation. Such a stress problem can seriously induce a leakage problem to the trench isolation and increase the parasitic capacitor thereof to decrease the response time of transistors.
It is therefore an object of this invention to provide a method for fabricating an integrated circuit using trench isolation that overcomes the above problems.
SUMMARY OF THE INVENTION
The invention may be incorporated into a method for fabricating trench isolation in an integrated circuit. A trench is etched at the desired region, and a sidewall insulator is provided. The wafer is then covered with a layer of deposited polycrystalline silicon, which also fills the trench. The polycrystalline silicon is then etched from the wafer surface (stopping on an underlying oxide layer), and is over-etched to create a recess in the plug to a predetermined depth. Thereafter, an oxide etch step is applied to remove a certain thickness of the sidewall oxide layer in order to expose the polycrystalline silicon edge in the opening of the trench. Then, the polycrystalline silicon inside the trench is oxidized to form a capping oxide layer on top of the recess by oxidizing the top and the exposed edge of the polycrystalline silicon film in the trench so that a uniform plug edge can be achieved inside the trench to prevent the stress and leakage problems induced by a wedge shaped oxide growing in the space between the plug and the substrate. Thus, it can eliminate the problems, such as the increase of stress, leakage current and transistor response time, as described in the prior art.
REFERENCES:
patent: 5770484 (1998-06-01), Kleinhenz
patent: 5783476 (1998-07-01), Arnold
patent: 5994200 (1999-11-01), Kim
Kao Ming-Kuan
Li Jui-Ping
Lin Hui-ching
Lin Ping-Wei
Bacon & Thomas
Mosel Vitelic Inc.
Tran Binh X.
Utech Benjamin L.
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