Method for improving thermal process steps

Details Method for improving thermal process steps Method for improving thermal process steps

2002-01-14

2004-03-16

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Recessed oxide by localized oxidation

C438S762000, C438S763000

Reexamination Certificate

active

06706616

ABSTRACT:

FIELD OF INVENTION
The invention relates to a method for improving thermal process steps in the patterning of semiconductor wafers, in particular in rapid thermal processing (RTP) processes preferably during AA (active area) oxidation, sacrificial oxidation, and GC (gate conductor) sidewall oxidation.
BACKGROUND
The oxides produced in these process steps are used, on the one hand, as screen oxides for the well implantations and, on the other hand, as an intermediate layer for reducing mechanical stress. The oxidation steps take place in a process chamber at relatively high process temperatures, with the result that the wafers are exposed to considerable thermal loading during these process steps, in particular in the case of high heating and cooling rates. The wafers are heated up to a stabilization step at 750° C., for example at 50° C./sec, and then up to the process temperature at a heating rate of 46° C./sec in the case of AA oxidation. The cooling rate may be 50° C./sec in the upper temperature range.
What are problematic are, in particular, the RTP processes in AA oxidation, sacrificial oxidation and in GC sidewall oxidation. The integrated gate stack, in particular, reacts sensitively to high heating rates.
The thermal loading occurring in this case can lead to lateral wafer distortions which result in uncorrectable positional errors of the structure planes lying one above the other, in particular of the contact hole planer. Positional errors above the other, in particular of the contact hole planes. Positional errors of this type did not occur with the hitherto customary structure widths of significantly more than 0.25 mm and the wafer material used.
With technologies of 0.25 mm for large scale integrated memory components, such positional errors in the contact hole planes, which also lead to DC yield losses, are no longer acceptable and can lead to significant losses of yield or even to the total functional incapability of entire batches.
SUMMARY
The invention is therefore based on the object of providing a method for improving thermal process steps in which the disadvantages described above are avoided.
In the case of a method of the type mentioned in the introduction, the formulation of the object on which the invention is based is achieved by virtue of the fact that the wafer is heated at a heating rate of approximately 12° C./sec up to a brief stabilization step at constant temperature and then up to the envisaged process temperature at a heating rate of 10° C./sec and, after the process time has elapsed, is cooled down to room temperature at a predetermined low cooling rate.
The stabilization step is preferably raised to a temperature of 120° C. below the process temperature and is 1000° C., for example.
With the reduction of the heating rate and the shifting of the stabilization temperature from hitherto 750° C. to 120° C. below the process temperature, the temperature response is homogenized over the wafer. As a result, wafer distortions no longer occur. oxidation processes, i.e. during AA oxidation, sacrificial oxidation and GC sidewall oxidation.
In a continuation of the invention, the wafer is cooled at a cooling rate of approximately 20° C./sec in the high-temperature range. This prevents wafer distortions from being able to occur during cooling.
Preferably, the wafer, at least in the temperature range in which wafer distortions can occur, is cooled at the cooling rate of approximately 20° C./sec from the process temperature to 120° below the process temperature.
Furthermore, it is advantageous if the flushing step at the start of the recipe is reduced to an extent such that the chamber is still sufficiently flushed with process gas and the cooling step at the end of the recipe is reduced to an extent such that the exit temperature is 600° C., with the overall result that the process time is reduced.


REFERENCES:
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patent: 5972779 (1999-10-01), Jang
patent: 99 03141 (1999-01-01), None
Moslehi, M.M., “Single-wafer optical processing of semiconductors: Thin insulator growth for intgrated electronic device applications”, Applied Physics A (Solids and Surfaces), Aug. 1988, vol. A46, No. 4, pp. 255-273.
Internation Search Report.

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