Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Patent
1996-01-30
1997-04-08
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
438631, 438941, 438926, H01L 21302, H01L 21304, H01L 21463
Patent
active
056187572
ABSTRACT:
Spin-on glass etchback is a technique commonly used to planarize the surface of a semiconductor wafer during fabrication. The etch rate of spin-on glass is largely affected by the amount of oxide exposed during the spin-on glass etchback process. The amount of oxide exposed during spin-on glass etchback is dependent upon the underlying pattern density of topography. A method of standardizing the pattern density of topography for different layers of semiconductor wafers to improve the spin-on glass etchback process used to planarize the surface of a wafer during processing is disclosed. In order to achieve a standardized pattern density of topography on the surface of a wafer, dummy raised areas are added into gaps between active conductive traces on a trace layer. In some embodiments, the standardized pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised areas are formed from a metallic material that is deposited in one single step with an oxide layer deposited over both the active conductive traces and the dummy raised areas prior to the application of spin-on glass and the spin-on glass etchback process. In other applications, the dummy raised areas are formed from an oxide material.
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Ichikawa, et al., "Multilevel Interconnect System for 0.35 um CMOS Lsi's with Metal Dummy Planarization Process and Thin Tungsten Wirings", Jun. 27-29, 1995 VMIC Conference, 1995 ISMIC--104/95/0254.
Bothra Subhas
Weling Milind G.
Bowers Jr. Charles L.
Gurley Lynne A.
VLSI Technology Inc.
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