Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-12-29
1999-03-02
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
H01L 213205, H01L 214763
Patent
active
058770747
ABSTRACT:
A method for improving the electrical property of gate in polycide structure is disclosed. First, a gate oxide layer is formed on the surface of the silicon substrate. The following procedure acts as one of the key points for the invention comprising the process steps of (1) forming a highly-doped polysilicon layer on the gate oxide, (2) forming an undoped amorphous silicon layer on the polysilicon layer, and followed by (3) forming a tungsten silicon layer on the amorphous silicon. Next, annealing at high temperature and in short time is performed. Such a stacked gate structure has low resistance and can solve the following problems: (1)peeling of tungsten silicide after annealing, (2) degradation of the electrical property of gate due to the diffusing and penetration of fluorine atoms coming from tungsten silicide.
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patent: 5554566 (1996-09-01), Lur et al.
patent: 5614428 (1997-03-01), Kapoor
patent: 5652156 (1997-07-01), Liao et al.
patent: 5710454 (1998-01-01), Wu
Chen Chun-Cho
Jeng Pei-Ren
Bowers Charles
Holtek Microelectronics Inc.
Liauh W. Wayne
Thompson Craig
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