Method for improving step coverage of dielectrics in VLSI circui

Details Method for improving step coverage of dielectrics in VLSI circui Method for improving step coverage of dielectrics in VLSI circui

1984-10-09

1986-07-22

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29591, 156646, 156653, 156657, 204192E, 357 71, 427 89, 427 93, B44C 122, C03C 1500, C03C 2506

Patent

active

046017810

ABSTRACT:
Particularly for use in multilevel metallization structures in which the underlying topography consists of fine and sharply contoured conductor lines produced by dry etching, conformal or near planar dielectric coatings are produced by depositing a dielectric layer to a thickness over the conductor of at least three times the conductor thickness. The dielectric is then anisotropically etched back to a thickness comparable with that of the underlying conductor. By this method a smooth dielectric top surface can be obtained without the requirement for multiple processing steps characterizing alternative planarizing techniques.

REFERENCES:
patent: 4377438 (1983-03-01), Moriya et al.
patent: 4524508 (1985-06-01), Sato

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