Semiconductor device manufacturing: process – Making device array and selectively interconnecting – With electrical circuit layout
Reexamination Certificate
2002-12-17
2004-11-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
With electrical circuit layout
C438S289000, C438S626000
Reexamination Certificate
active
06812069
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to methods for chemical mechanical polishing (CMP) and more particularly to a method for forming dummy features within selected portions of a semiconductor wafer including die to improve polishing uniformity in a CMP process and avoid fracture of a dielectric insulating layer.
BACKGROUND OF THE INVENTION
Sub-micron multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Planarization is increasingly important in semiconductor manufacturing techniques. As device sizes decrease, the importance of achieving high resolution features through photolithographic processes correspondingly increases thereby placing more severe constraints on the degree of planarity required of a semiconductor wafer processing surface. Excessive degrees of surface non-planarity will undesirably affect the quality of several semiconductor manufacturing process including, for example, photolithographic patterning processes, where the positioning the image plane of the process surface within an increasingly limited depth of focus window is required to achieve high resolution semiconductor feature patterns.
Chemical mechanical polishing (CMP) is increasingly being used as a planarizing process for semiconductor device layers, especially for devices having multi-level design and smaller semiconductor fabrication processes, for example, having line widths below about 0.25 micron. CMP planarization is typically used several different times in the manufacture of a multi-level semiconductor device, including planarizing levels of a device containing both dielectric and metal portions to achieve global planarization for subsequent processing of overlying levels. For example, CMP is used to remove excess metal after filling conductive metal interconnect openings formed in dielectric insulating layers with metal to form features such as vias and trench lines. The vias and trench lines electrically interconnect the several levels and areas within a level that make up a multi-level semiconductor device.
Several semiconductor feature defects can be associated with CMP polishing. For example, in CMP polishing of a high polish rate materials such as an insulating dielectric material or soft metal such as copper, uniform polishing or local planarization is highly dependent on feature surface area and density. For example, the material removal rate is proportionally faster with the surface area of the high polish rate material leading to dishing. In addition, for low polish rate materials such as metal nitrides or carbides, a high metal pattern density (smaller pitch) adjacent to low polish rate materials such as nitrides can lead to erosion. The effect of non-uniform material removal whether due to dishing or erosion results in non-uniform topographies over the wafer surface thereby detrimentally affecting subsequent processes such as photolithographic patterning and feature etching. For example, wide areas of metal patterning such as bonding pads and wide interconnect metal lines as well as to a relatively high density of metal interconnect lines (trench lines), for example, in damascene structure metallization layers, can lead to local non-uniformities due to dishing or erosion. Polishing non-uniformity is frequently present within individual die and is frequently referred to as within-die (WID) non-uniformity. For example, such WID non-uniformity can lead to excess removal of wide area metal interconnects and bonding pads adversely affecting subsequent processes and electrical inter-connectivity.
One approach to improve WID uniformity has been to introduce dummy features, for example dummy features in relatively featureless areas of a die. In the prior art rectangular shaped features have been used since they are easily patterned and formed in parallel with active areas such as rectangular bonding pads. For example, rectangular dummy features about 3 microns to about 5 microns on an edge are provided surrounding wide area metal features such as bonding pads in otherwise relatively featureless areas to improve the overall polishing uniformity between the relatively dense feature areas and relatively featureless areas within the die. One problem with the prior art method of producing rectangular shaped dummy features is the tendency for stress fields created by an applied load, for example during CMP polishing, to concentrate at the corners of such features. As a result of the concentration of stress force fields at sharply directionally divergent material interface contours (corners), such as rectangular metal filled dummy features formed in a dielectric insulating layer, the fracture strength of the dielectric insulating layer is exceeded at the corner areas of the dummy features, causing the initiation and catastrophic propagation of cracks, also known a brittle fracture, through the dielectric insulating layer.
The problem is exacerbated by the use of low-k (low dielectric constant) material used for the dielectric insulating layers also referred to as inter-metal dielectric (IMD) layers, for example, having a dielectric constant less than about 3.2. Many of the low-k materials are designed with a higher degree of porosity or made of organic materials with less robust mechanical properties to allow the achievement of lower dielectric constants. A shortcoming of using low-k materials is that the less robust mechanical properties of the low-k IMD layers, such as strength and hardness, make the low-k IMD layers more susceptible to brittle fracture compared to traditional higher k materials such as silicon dioxide. For example, low-k materials are more prone to brittle fracture at a given applied load or when stressed a given amount, for example, when a semiconductor wafer process is subjected to stresses induced by CMP processes.
There is therefore a need in the semiconductor processing art to develop a method to improve CMP polishing uniformity whereby fracturing or cracking of low-k dielectric insulating layers including dummy semiconductor features can be reduced or prevented during the application of loads such as those attributable to CMP processes.
It is therefore an object of the invention to provide a method to improve CMP polishing uniformity whereby fracturing of low-k dielectric insulating layers including dummy semiconductor features can be reduced or prevented during the application of loads such as those attributable to CMP processes while overcoming other shortcomings and deficiencies in the prior art.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a method for improving CMP polishing uniformity and reducing or preventing cracking in a semiconductor wafer process surface by reducing stress concentrations adjacent to dummy features.
In a first embodiment, the method includes providing a semiconductor wafer process surface including active features and dummy features formed adjacently to the active features to improve a CMP polishing uniformity said dummy features each shaped to define an enclosed area in said semiconductor wafer process surface plane comprising at least 5 corner portions; and, performing a CMP process on said semiconductor wafer process surface.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
REFERENCES:
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Jang Syun-Ming
Tseng Tung-Ching
Yao Chih-Hsiang
Lindsay Jr. Walter L.
Niebling John F.
Taiwan Semiconductor Manufacturing Co. Ltd
Tung & Associates
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